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參數資料
| 型號： | TS68C429AVR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT |
| 中文描述： | 3 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數： | 19/43頁 |
| 文件大?。?/td> | 1638K |
| 代理商： | TS68C429AVR |
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TS68C429A
2120A–HIREL–08/02
Gap Register (Figure 12)
The gap register is accessible for writing operations only. It contains the value on which
the gap counter will be stopped and will generate the end of the message signal (see
“Inputs” on page 14). The value is interpreted as a multiple of the CLK ARINC period.
Figure 12.
Gap Register Description
The value of the gap register must be chosen so as to generate the end of the message
before the minimal gap as defined in the ARINC-429 norm.
Message Buffer
The Buffer is made of two 16-bit registers, the Most Significant Word of the message
(MSW) is contained in the lower address register, the Least Significant Word of the mes-
sage (LSW) is contained in the upper address register. For correct behavior, the MSW
must be read before the LSW. They are accessible in read mode only and 16-bit access
is mandatory.
Label Control Matrix
The label control matrix is a 256 x 1 bit memory. There is one memory per channel.
The address is driven by the incoming label, the output data is used to validate this
incoming message label (see Figure 13). To program this matrix, the LCMWE (label
control matrix write enable) bit of the receiver-control-register should be set to “1” to
allow the access. At this time, the address is driven by the external address bus and the
data are written from the data bus D7 to D0 (one per channel according to Figure 14).
Any write to a matrix on which the LCMWE is not set will not have any effect. The label
control matrix can be written or read in byte and word mode. In word mode, the state of
D15-D8 is unknown. After complete programming of the matrix, the LCMWE bit should
be reset to “0” to allow normal receiving mode. A “1” in the memory means that this label
is allowed and a “0” means that this label must be ignored.
Bit 5
Not used
Bit 4
Not used
Bit 0 to 3
Channel priority: order
The lowest value will give the highest priority. Each channel must have a unique
channel priority order.
If several messages are pending, the interrupt vector will account for highest priority
channel.
Table 9.
Register Control Register Description
Bit
Function
Comments
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| TS68C429ADESCxx | CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT |
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相關代理商/技術參數 |
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| TS68C429AVRA | 制造商:e2v Aerospace & Defense 功能描述:Multi Channel Receiver/Transmitter 84-Pin PGA 制造商:e2v technologies 功能描述:MULTI CH RCVR/TRANSMITTER 84PIN PGA - Trays |
| TS68EN360 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-bit Quad Integrated Communication Controller |
| TS68EN360DES01MXAL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-bit Quad Integrated Communication Controller |
| TS68EN360DES01MXCL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-bit Quad Integrated Communication Controller |
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