參數(shù)資料
型號(hào)： TPS68000DBTRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： FLUORESCENT LIGHT CONTROLLER, 100 kHz SWITCHING FREQ-MAX, PDSO30
封裝： GREEN, PLASTIC, TSSOP-30
文件頁(yè)數(shù)： 9/25頁(yè)
文件大?。?/td> 981K
代理商： TPS68000DBTRG4
www.ti.com
R
FAULT +
V
LOGIC
0.5 mA
(1)
Main Oscillator
R
SET +
9720
kW
kHz
f
N
(2)
Synchronization of the Main Oscillator
f
N + VPH
90
o
V
(3)
Startup and Wait Timing
t
SW + CSTC
0.42
s
mF
(4)
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
RFAULT is the minimum resistance value of the pullup resistor, VLOGIC is the maximum supply voltage of the logic
connected to FAULT.
In normal operation the controller operates at the frequency of the main oscillator. It is programmed with a
resistor connecting the SET pin to GND. The resistor value is calculated using Equation 2:
If the controller should be synchronized to an external clock the main oscillator frequency should be programmed
close to the synchronizing frequency. This avoids large variations in case external clock pulses are missing. It
also speeds up the locking to the external clock. The SET pin should never be left open.
The main oscillator can be used in different modes of operation. The first and most important mode is using it as
a reference clock. This is also the mode of choice in a single controller application which is not synchronized to
an external clock. In this mode the SYNC pin is used as an output and should be left open if no circuit needs to
be synchronized to the device main oscillator clock. To force the device operating in this mode 5 V (V5) must be
connected to the PH pin.
Lower voltages applied at the PH pin configure the SYNC pin as an input. Detailed voltage levels for this can be
found in the electrical characteristics table. If the SYNC pin is configured as an input the device automatically
synchronizes the main oscillator to the frequency which must be applied at the SYNC pin. The compensation for
this main oscilator PLL circuit is done with a capacitor connected at the STC pin. Since this capacitor is used for
defining sweep and wait timing during startup and voltage regulation, synchronization is only possible when the
device has started and is regulating lamp current. Any capacitance value which makes sense for defining sweep
and wait time should offer a reasonable compensation for the main oscillator PLL. How to calculate the value for
the capacitor at STC to program the startup and wait timing is shown in the following paragraph. Typical values
are in a
F range.
Also a phase shifted synchronization can be programmed. For this a voltage in the range between 0 V and 2 V
must be applied at the PH pin. For calculating the phase shift of the main oscillator clock to the clock applied at
the SYNC pin Equation 3 can be used:
In this equation
φ
N is the main oscillator clock phase shift and VPH is the voltage applied at the PH pin.
After enabling the device the device is starting at double the programmed main oscillator frequency and is
sweeping down to half the programmed main oscillator frequency. The timing for the sweep is programmed with
a capacitor connected between STC and GND. It can be calculated using Equation 4:
tSW is the sweep time and CSTC is the capacitance connected between the pins STC and GND.
If at any time the voltage regulator becomes active a wait timer is started. The timing is also programmed with a
capacitor connecting STC and GND. Open lamp condition will lead to shutdown after timeout. Equation 5 shows
how to calculate the wait time, tW:
17
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