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參數(shù)資料
| 型號(hào)： | TPS68000DBTRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | FLUORESCENT LIGHT CONTROLLER, 100 kHz SWITCHING FREQ-MAX, PDSO30 |
| 封裝： | GREEN, PLASTIC, TSSOP-30 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 981K |
| 代理商： | TPS68000DBTRG4 |
www.ti.com
Phase Shifted Burst Dimming
f
B + VPH
180
o
V
(15)
Layout Considerations
THERMAL INFORMATION
P
D(MAX) +
T
J(MAX) * TA
R
q
JA
+
125oC * 85oC
63.9
o
C
W
+ 626 mW
(16)
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
The device also supports phase shifted burst dimming. In this configuration a direct PWM burst signal is used
which must be connected to BC. The internal low frequency oscillator must be programmed as described in the
independent burst dimming section and in Equation 13. Since the internal low frequency oscillator will be
synchronized to the frequency connected to BC it is recommended to program the internal low frequency close to
the frequency at BC. The synchronization is done using a PLL circuit. This PLL circuit needs an external
compensation network connected at BBR. For a typical burst frequency in the 100 Hz range using a 0.68
F
capacitor in series with a 100 k
resistor is recommended. This R - C network should be connected between
BBR and GND.
The phase shift of the dimming burst compared to the input signal at BC is programmed with a voltage applied at
PH. The resulting phase shift can be calculated using Equation 15:
φ
B is the phase shift of the dimming burst and VPH is the voltage applied at the PH pin.
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. Use a common ground node for power ground and a different one for control ground to minimize the
effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To layout the control ground, it is recommended to use short traces as well, separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS68000 device is 125°C. The thermal resistance
of the 30-pin TSSOP package (PW) is RθJA = 63.9°C/W. Specified regulator operation is assured to a maximum
ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 626 mW. More power can
be dissipated if the maximum ambient temperature of the application is lower.
20
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