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參數(shù)資料
| 型號： | TPS65820RSHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, QFN-56 |
| 文件頁數(shù)： | 84/98頁 |
| 文件大小： | 2290K |
| 代理商： | TPS65820RSHT |
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General Purpose I/Os — GPIO 1, 2, 3
GPIOs Input Level Configuration
S1
S2
D
C
ENB
Multiplexer
Q
SET
CLR
D
GPIO
SignalPin
HI=RisingEdge,
LO=FallingEdge
UVLO
GPIOConfig= OUTPUT
Equivalentcircuitforinternal
logicwhenconfiguredasedge
interruptwithnomasking
I CINTACKREAD
C
2
ommand?
INT
www.ti.com .............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The TPS65820 integrates 3 general purpose open drain ports (GPIOs) that can be configured as selectable
inputs or outputs. When configured as outputs the output level can be set to LO or HI via I2C commands. When
the GPIOs are configured as inputs the action to be taken when a transition or HI/LO level is detected at the
GPIO pin is selectable via I2C.
When configured as inputs the GPIOs can be set in the following modes:
1. Interrupt request: In this mode of operation, a transition at the GPIO pin generates an interrupt request at the
interrupt controller. The GPIO interrupt request can be masked at the INT_MASK register. This operation
mode is available for GPIOs 1 and 2.
2. SM1 and SM2 control: The GPIOs can be used to turn the converters SM1 and SM2 ON/OFF, as well as
setting them in standby mode. This control mode is available for GPIO1 (SM1 on/off and SM1/SM2 standby)
and GPIO2 (SM2 on/off control).
3. ADC trigger : GPIO3 can be configured as an external ADC trigger. The GPIO3 trigger configuration bit is
located at the ADC register ADC_DELAY.
When using I2C commands, the GPIO1 and GPIO2 pins can be configured as logic output signals or as
level-controlled inputs which enables (or disables) the switch mode converters SM1 and/or SM2. These pins may
also be configured as rising- or falling-edge-triggered inputs to externally control the generation of an interrupt
signal (INT), if desired.
The GPIO3 pin may be used as an external trigger source to start an A/D conversion cycle or as a logic output.
See Figure 59 for a description of the logic used for GPIO1 and GPIO2 inputs when configured for
edge-triggered interrupt generation. The signal from the GPIO pin input is double-latched before being sent to the
interrupt contoller logic. The inversion of the Q output from the first flip-flop must be HI to allow the output latch to
be cleared when a READ command occurs. On the initial edge of the GPIO signal, the Q output of the flip-flop is
set (HI). The INT line is asserted (LO) after the initial selected edge from the GPIO pin. On the next falling (or
rising) edge of the GPIO pin, the interrupt can again be cleared (which allows the INT pin to go back high). The
INT signal is cleared (set back HI) after an I2C READ operation is performed.
Thus, two successive edges of the GPIO signal, followed by an I2C READ command, are required to clear the
INT pin output. If no I2C READ commands occur, repeatedly applying edges to the GPIO pin does not toggle the
state of the INT pin output.
In addition to an I2C READ command after two GPIO edges, a UVLO event or reconfiguration of the GPIO pins
as outputs also de-asserts the INT signal.
Figure 59. GPIO 1 or GPIO2 Configured as an Interrupt Request Input
Copyright 2006–2008, Texas Instruments Incorporated
85
Product Folder Link(s): TPS65820
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