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參數(shù)資料
| 型號： | TPS65820RSHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, QFN-56 |
| 文件頁數(shù)： | 68/98頁 |
| 文件大?。?/td> | 2290K |
| 代理商： | TPS65820RSHT |
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External Trigger Operation
Detecting an External Trigger Event
GPIO3
INTERNAL ADC
CONVERSIONSTART
CONVERTER
MODE
ARMED
CONVERTING
TDLY(TRG)
Executing Multiple Sample Cycles With an External Trigger
SLVS663B – MAY 2006 – REVISED APRIL 2008 .............................................................................................................................................................. www.ti.com
The value loaded in the I2C registers ADC READING_HI and ADC READING_LO at the end of a conversion
cycle is defined by control bits ADC_READ0 and ADC_READ1 in register ADC READING_HI. The average,
minimum, maximum and last sample values for a conversion cycle can be read if the external host executes an
I2C write operation, changing the values of bits ADC_READ0 and ADC_READ1, followed by an I2C read
operation on registers ADC READING_HI and ADC READING_LO. The minimum, maximum, average, and last
values have the same value if a conversion cycle with only one sample is executed.
The ADC_READ0 and ADC_READ1 bits can not be modified during the execution of a conversion cycle. A new
conversion cycle should be started only after the current conversion cycle is completed, by toggling the ADC_EN
bit from HI to LO and HI again.
The trigger control circuit can be programmed to use an external signal to start a conversion. The TPS65820
GPIO3 input is configurable as an ADC trigger, with ADC conversion starting on either a rising edge or falling
edge. When using an external trigger the trigger delay, trigger wait time delay and trigger holdoff mode can be
programmed using I2C registers.
The procedure to start an externally-triggered conversion cycle has the following steps:
1. Verify that the current conversion cycle has ended (ADC_STATUS=LO, I2C register ADC_READING_HI)
2. Set ADC_EN=LO
3. Configure ADC sampling mode, ALU mode, trigger parameters, etc.
4. Set ADC_EN=HI
After step 4 the ADC is armed, waiting for an external trigger detection to start a conversion cycle. Similarly to
the non-triggered mode, the ADC configuration should not be modified until the current conversion cycle ends.
Note that in the external trigger mode the current cycle does not end if the converter is armed and an external
trigger is not detected.
An external trigger event is detected when the GPIO3 input has an edge that matches the edge detection
programmed in the EDGE bit, at the I2C register ADC_DELAY. The internal ADC trigger can be delayed with
respect to the external trigger signal edge. The delay time value is set by the ADC_DELAY register bits
DELAY_n, and can range from 0
s (no delay) to 750 s. A conversion is started only if the external trigger
remains at its active level when the delay time expires, as shown in Figure 49. In a positive-edge detection the
active trigger level is HI; in a negative-edge detection the active trigger level is LO.
Figure 49. ADC Conversion Triggerd by GPIO3 Positive Edge Triggered Active Level Hi
When executing conversion cycles that require multiple samples it may be desirable to synchronize the input
signal conversion using either an external trigger that has a periodic repetition rate or an external asynchronous
trigger that indicates when the external input signal being converted is valid. The TPS65820 has additional
operating modes and timing parameters that can be programmed using the I2C to configure multiple sample
conversion cycles.
In multiple sample cycles the host can select the wait time between samples using the bits WAITn in the
ADC_WAIT register to set the wait time between samples. The wait time is measured between the end of a
conversion and the start of a new conversion.
70
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
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