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參數(shù)資料
| 型號： | TPS2491DGSG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 925K |
| 描述： | IC POS HV HOT-SWAP CTRLR 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 80 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 9 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 配用： | 296-18947-ND - EVAL MODULE FOR TPS2491-002 |
LIM
+
50 mV
R
TPS2490
TPS2491
www.ti.com
SLVS503D NOVEMBER 2003REVISED JULY 2012
DETAILED PIN DESCRIPTION
The following description relies on the Typical Application and Corresponding SOA circuit, and the functional
block diagram.
VCC: This pin is associated with three functions: 1) biasing power to the integrated circuit, 2) input to power on
reset (POR) and under voltage lockout (UVLO) functions, and 3) voltage sense at one terminal of R
S
for M1
current measurement. The voltage must exceed the POR (about 6 V for approximately 400 約) and the internal
UVLO (about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be
designed to minimize R
S
voltage sensing errors and to maximize the effect of C1 and D1; place C1 at R
S
rather
than at the IC pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either
UVLO or POR are active.
SENSE: Monitors the voltage at the drain of M1, and the downstream side of R
S
providing the constant power
limit engine with feedback of both M1 current (I
D
) and voltage (V
DS
). Voltage is determined by the difference
between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant
power engine uses V
DS
to compute the allowed I
D
and is clamped to 50 mV, acting like a traditional current limit
at low V
DS
. The current limit is set by the following equation:
(1)
Design the connections to SENSE to minimize R
S
voltage sensing errors. Don't drive SENSE to a large voltage
difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by
connecting SENSE to VCC.
GATE: Provides the high side (above VCC) gate drive for M1. It is controlled by the internal gate drive amplifier,
which provides a pull-up of 22 糀 from an internal charge pump and a strong pull-down to ground of 75 mA
(min). The pull-down current is a non-linear function of the amplifier overdrive; it provides small drive for small
overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut
M1 off when EN or UVLO cause this to happen. An internal clamp protects the gate of M1 (to OUT) and
generally eliminates the need for an external clamp in almost all cases for devices with 20 V V
GS(MAX)
ratings; an
external Zener may be required to protect the gate of devices with V
GS(MAX)
< 16 V. A small series resistance
(R5) of 10 & should be inserted in the gate lead if the C
ISS
of M1 > 200 pF, otherwise use 33 & for small
MOSFETs.
A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile
without affecting the amplifier stability. Add a series resistor of about 1 k& to the gate capacitor to maintain the
gate clamping and current limit response time. Adding capacitance across M1 gate to source requires some
series damping resistance to avoid high-frequency oscillations.
OUT: This input pin is used by the constant power engine and the PG comparator to measure V
DS
of M1 as
V
(SENSE-OUT).
Internal protection circuits leak a small current from this pin when it is low. If the load circuit can
drive OUT below ground, connect a clamp (or freewheel) diode such as an S1B from OUT (cathode) to GND
(anode).
EN: The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds
have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by
R1/R2 in the Typical Application and Corresponding SOA circuit, or it can be tied to VCC to always enable the
TPS2490/91. The hysteresis associated with the internal comparator makes this a stable method of detecting a
low input condition and shutting the downstream circuits off. A TPS2490 that has latched off can be reset by
cycling EN below its negative threshold and back high.
VREF: Provides a 4.0-V reference voltage for use in conjunction with R3/R4 of the typical application circuit to
set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds
have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA
is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be
placed on this pin.
PROG: The voltage applied to this pin (0.4 4 V) programs the power limit used by the constant power engine.
Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to the
following equation:
Copyright ?20032012, Texas Instruments Incorporated
9
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