參數(shù)資料
型號: TPS2491DGSG4
廠商: Texas Instruments
文件頁數(shù): 17/25頁
文件大?。?/td> 925K
描述: IC POS HV HOT-SWAP CTRLR 10-MSOP
標(biāo)準(zhǔn)包裝: 80
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: 9 V ~ 80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
配用: 296-18947-ND - EVAL MODULE FOR TPS2491-002
TPS2490
TPS2491
www.ti.com
SLVS503D NOVEMBER 2003REVISED JULY 2012
Faults and Backplane Voltage Droop
A hard short at the output of the TPS2490/91 during normal operation could result in activation of the enable or
UVLO circuit instead of the current limit if the input voltage droops sufficiently. The lower GATE drive in this
condition will cause a prolonged, larger over-current spike. This can be eliminated by filtering EN, or distributing
capacitance on the bus itself. Capacitance from adjacent plugged-in units may help with this as well.
Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current limit. The OUT pin ratings can be maintained with a small diode, such as an S1B, across TPS2490/91
OUT to GND.
Gate Clamp Diode
The TPS2490/91 has a relatively well-regulated gate voltage of 1216 V, even with low supply voltages. A small
clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if V
GS
of M1 is rated below this.
High Gate Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1
exceeds about 4000 pF. When gate capacitor dv/dt control is used, a 1-k& resistor in series with C
G
is
recommended. If the series R-C combination is used for MOSFETs with C
ISS
less than 3000 pF, then a Zener is
not necessary.
Input Bypass
C1 should be present for control of external noise at VCC and as a low-impedance source for high-speed
circuits.
Output Short Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to obtaining different results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheetevery setup differs.
Layout Considerations
Good layout practice places the power devices D1, R
S
, M1, and C
O
so power flows in a sequential fashion, and
preferably in a straight line. A ground plane under the power and the TPS2490/91 is desirable. The TPS2490/91
should be placed close to the sense resistor and the MOSFET; a Kelvin connection is recommended to achieve
accurate current sensing across R
S
. A low-impedance GND connection is required because the TPS2490/91 can
momentarily sink upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active,
so keep the gate trace length short. The PROG, TIMER, and EN pins have high input impedances, therefore
keep their input leads short. Oversize power traces and power device connections to assure low voltage drop
and good thermal performance.
Copyright ?20032012, Texas Instruments Incorporated
17
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