參數(shù)資料
型號(hào): TPS2491DGSG4
廠商: Texas Instruments
文件頁數(shù): 11/25頁
文件大?。?/td> 925K
描述: IC POS HV HOT-SWAP CTRLR 10-MSOP
標(biāo)準(zhǔn)包裝: 80
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: 9 V ~ 80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
配用: 296-18947-ND - EVAL MODULE FOR TPS2491-002
VCCCH1
VCC10V/div
Timer1V/div
I
IN
1A/div
PG
10V/div
OUT
10 V/div
-
-
TPS2490
TPS2491
www.ti.com
SLVS503D NOVEMBER 2003REVISED JULY 2012
APPLICATION INFORMATION
BASIC OPERATION
The TPS2490/91 provides all the features needed for a positive hotswap controller. These features include: 1)
under-voltage lockout; 2) adjustable (system-level) enable; 3) turn-on inrush limit; 4) high-side gate drive for an
external N-channel MOSFET; 5) MOSFET protection (power limit and current limit); 6) adjustable overload
timeoutalso  called  an  electronic  circuit  breaker;  7)  charge-complete  indicator  for  downstream  converter
coordination; and 8) an optional automatic restart mode. The TPS2490/91 features superior power-limiting
MOSFET protection that allows independent control of current limit (to set maximum full-load current), power limit
(to control junction temperature rise), and overload time (to control case temperature rise).
The typical application circuit, and oscilloscope plots of Figure 13 through Figure 17 demonstrate many of the
functions described above.
Board Plug-In (Figure 13)
Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in.
The TPS2490/91 is held inactive, and GATE, PROG, TIMER, and PG are held low for less than 1 ms while
internal voltages stabilize. A startup cycle is ready to take place after the stabilization.
GATE, PROG, TIMER, and PG are released after stabilization in this example because both the internal UVLO
threshold and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from
the GATE pin and M1 begins to turn on while the voltage across it, V
(SENSEOUT)
, and current through it,
V
(VCCSENSE)
, are monitored. Current initially rises to the value which satisfies the power limit engine (P
LIM
?V
VCC
)
since the output capacitor was discharged.
TIMER and PG Operation (Figure 13)
The TIMER pin charges C
T
as long as limiting action continues, and discharges at a 1/10 charge rate when
limiting stops. If the voltage on C
T
reaches 4 V before the output is charged, M1 is turned off and either a latch-
off or restart cycle commences, depending on the part type. The open-drain PG output provides a deglitched
end-of-charge indication which is based on the voltage across M1. PG is useful for preventing a downstream
dc/dc converter from starting while C
O
is still charging. PG goes active (open drain) about 9 ms after C
O
is
charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the converter
starts up. The resistor pull-up shown on pin PG in the typical application diagram only demonstrates operation;
the actual connection to the converter depends on the application. Timing can appear to terminate early in some
designs if operation transitions out of the power limit mode into a gate charge limited mode at low V
DS
values.
Figure 13. Basic Board Insertion
Copyright ?20032012, Texas Instruments Incorporated
11
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