參數(shù)資料
型號(hào)： TPS24711DGSR
廠商： Texas Instruments
文件頁(yè)數(shù)： 24/34頁(yè)
文件大?。?/td> 2792K
描述： IC CTRLR HOT SWAP 2.5-18V 10MSOP
標(biāo)準(zhǔn)包裝： 1
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無(wú)
電流限制： 可調(diào)
電源電壓： 2.5 V ~ 18 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 296-28562-6
T
FLT
T
10 A
=
t    ,
1.35 V
herefore,
10 A
=
7 ms   52 nF
1.    V
?/DIV>
?/DIV>
=
ISS
FLT
ON
GATE
FLT
5.9 V  C
t
,
I
herefore,
5.9 V  2040 pF
0.614 ms
1.22 ms
2    A
?/DIV>
=
+
?/DIV>
=
+
=
ON
=
2
OUT
VCC(MAX)
OUT
VCC(MAX)
OUT
LIM
LIM    LIM
VCC(MAX)
2
LIM
LIM
LIM
C
V
C
V
C
P
if   P
I
V
2  P
I
2  I
?/DIV>
?/DIV>
?/DIV>
+
-
<
?/DIV>
?/DIV>
?/DIV>
OUT
VCC(MAX)
LIM    LIM
VCC(MAX)
LIM
C
V
if   P
I
V
I
?/DIV>
>
?/DIV>
(    )
2
ON
2
herefore,
470 F   12 V
470 F  29.3 W
470 F  12 V
0.614 ms
2  29.3 W
12 A
2   12 A
?/DIV>
?/DIV>
?/DIV>
=
+
-
=
?/DIV>
?/DIV>
TPS24710,TPS24711
TPS24712,TPS24713
SLVSAL2E JANUARY 2011REVISED NOVEMBER 2013
www.ti.com
STEP 4. Choose Output Voltage Rising Time, t
ON
, C
T
The maximum output voltage rise time, t
ON
, set by the timer capacitor C
T
must suffice to fully charge the load
capacitance C
OUT
without triggering the fault circuitry. Equation 10 defines t
ON
for two possible inrush cases.
Assuming that only the load capacitance draws current during start-up,
(10)
The next step is to determine the minimum fault-timer period. In Equation 10, the output rise time is t
ON
. This is
the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer
uses the difference between the input voltage and the gate voltage to determine if the TPS24710/11/12/13 is still
in inrush limit. The fault timer continues to run until V
GS
rises 5.9 V (for V
VCC
= 12 V) above the input voltage.
Some additional time must be added to the charge time to account for this additional gate voltage rise. The
minimum fault time can be calculated using Equation 11,
(11)
where  C
ISS
is  the  MOSFET  input  capacitance  and  I
GATE
is  the  minimum  gate  sourcing  current  of
TPS24710/11/12/13, or 20 糀. Using the example parameters in Equation 11 and the CSD16403Q5 data sheet
(SLPS201) leads to a minimum fault time of 1.22 ms. This time is derived considering the tolerances of C
OUT
,
C
ISS
, I
LIM
, P
LIM
, I
GATE
, and V
VCC(MAX)
. The fault timer must be set to a value higher than 1.22 ms to avoid turning
off during start-up, but lower than any maximum fault time limit determined by the SOA curve (see Figure 35)
derated for operating junction temperature.
For this example, select 7 ms to allow for variation of system parameters such as temperature, load, component
tolerance, and input voltage. The timing capacitor is calculated in Equation 4 as 52 nF. Selecting the next-highest
standard value, 56 nF, yields a 7.56-ms fault time (see Equation 12).
(12)
24
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Copyright ?20112013, Texas Instruments Incorporated
Product Folder Links: TPS24710  TPS24711 TPS24712  TPS24713
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