參數(shù)資料
型號: TPS2346PWRG4
廠商: Texas Instruments
文件頁數(shù): 27/30頁
文件大小: 490K
描述: IC HOT SWAP POWER MGR 24-TSSOP
標(biāo)準(zhǔn)包裝: 2,000
類型: 熱交換控制器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)(ONET)
內(nèi)部開關(guān):
電源電壓: -5.2V,3.3V,5V,5.15V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
TPS2346
 
SLUS529  MAY 2002
27
www.ti.com
APPLICATION INFORMATION
layout considerations
To optimize the performance of the TPS2346, care should be taken to use good layout practice with the parts
placement and etch routing of the hot swap circuit components. This includes any protection devices as well
as the sense and pass elements. Protection devices should be located close to the hot swap controller, and
trace-lengths back to their respective pins kept to a minimum. If a decoupling capacitor is used on the VIN1
supply, it also should be placed close to the part.
Mount the charge pump reservoir capacitor (C6 in the application diagram) close to the TPS2346, with minimal
trace lengths back to the CPUMP and CPGND pins.
For proper operation, the three ground pins of the TPS2346 must be connected together near the device. The
ground leads of the ramp and charge pump capacitors, protection diodes, and any decoupling capacitors should
also tie into this node close to the part. This junction should be routed separately back to the J1 connector, where
it can tie into the PCB GND node, as opposed to tying into the ground plane elsewhere in the high-current return
path.
Use wide traces when connecting the sense resistors and power FETs into their respective current paths. When
feeding these connections through from an internal power plane, use multiple vias to reduce the overall
impedance of the current path. This helps reduce insertion loss across the hot swap interface, and improve the
thermal performance of the PCB. Additional copper plane used on the land patterns of these devices can
significantly reduce their thermal impedance, reducing temperature rise in the module and improving overall
reliability of the power devices.
Connections to the sense resistors for the VINx and CSx device pins should be made with good Kelvin
connections to optimize the accuracy of the current-limit thresholds and slew-rate control. This is especially
important on high-current supplies. When typical load levels on these supplies are high, board trace resistance
between elements in the supply current paths becomes significant. The two sense traces for each supply should
connect symmetrically to the sense resistor land pattern, in close proximity to the element leads, and not
upstream or downstream from the device. Trace routing back to the TPS2346 should be fairly well balanced.
Figure 22 illustrates two recommendations for the current sense layout.
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