參數資料
型號: TPS2346PWRG4
廠商: Texas Instruments
文件頁數: 24/30頁
文件大小: 490K
描述: IC HOT SWAP POWER MGR 24-TSSOP
標準包裝: 2,000
類型: 熱交換控制器
應用: 光纖學網絡(ONET)
內部開關:
電源電壓: -5.2V,3.3V,5V,5.15V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 帶卷 (TR)
TPS2346
 
SLUS529  MAY 2002
24
www.ti.com
APPLICATION INFORMATION
To complete the design of the power interface for the plugin shown in the typical application diagram, assume
that a maximum slew rate of 1.5 A/ms is specified for each of the three positive-voltage loads. A value for
capacitor C2 must still be determined. Inspection of equation (4) indicates that, given the same di/dt requirement
on all supplies, the supply channel(s) with the lowest-value sense resistor dictates the minimum value for the
IRAMP capacitor. Therefore, the 5-V and 3.3-V supplies are suggested in this case for obtaining an initial
estimate for C
IRAMP
. Using the associated values, equation (4) produces the result shown in equation (5).
C
IRAMP2,3
+
68
67.5
(
0.002 W
)
 
1500 As
^ 0.336 mF
A value of 0.33 礔 can be used, or the next available standard value of 0.39 礔 provides some margin for
capacitor and sense-resistor tolerances. In either case, equation (4) can be rewritten as equation (6), which is
used here to verify that the 5.15-V slew rate is still within specification.
didt
x
+
68
67.5 R
SNSx
  C
IRAMPx
where:
R
SNSx
 is in ohms,
C
IRAMPx
 is the value suggested by equation (5) in microfarads, and
(di/dt)
x
 is given in amps/second.
For a C
IRAMP
 of 0.39 礔, the maximum di/dt for the 5.15-V supply is approximately 860 mA/ms which is well
within the example requirement.
protection against faulted loads
The TPS2346 allows the time period of one IRAMP pulse for each back-end planes voltage to ramp-up to its
minimum level. After this delay period, the device latches off if an undervoltage fault is subsequently detected.
This nominal delay time, t
TIMER
, is set by the constant-current charging and subsequent discharging of C
IRAMP
,
and is therefore determined from equation (7).
t
TIMER
+ C
IRAMP
  1.4
1
58
)
1
1.8
where:
C
IRAMP
 is in microfarads.
The resultant fault timer period should be sufficient for most applications; however, it is good design practice
to verify that the delay is long enough for each load.
(5)
(6)
(7)
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