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參數資料
| 型號： | TNETA1610 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| 中文描述： | STS-12c/STM-4接收器/發(fā)射器的時鐘恢復/代（STS-12C/STM-4接收/傳送器） |
| 文件頁數： | 6/10頁 |
| 文件大?。?/td> | 215K |
| 代理商： | TNETA1610 |
TNETA1610
STS-12c/STM-4 RECEIVER/TRANSMITTER
WITH CLOCK RECOVERY/GENERATION
SDNS037 – SEPTEMBER 1995 – REVISED MARCH 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 1. Data/Clock Source Control (Continued)
STATE OF INPUTS
SOURCE OF DATA/CLOCK FOR OUTPUTS
OE
FLB
CLKLOOP
CKGENBP
CKRECBP
TSDT/TSDC
TSCT/TSCC
TPCK
RPD0-RPD7
RPCK
1
0
0
1
1
TPD0–TPD7
TXHCKT/
TXHCKC
Receive
recovered
RSCT/RSCC
TXHCKT/
TXHCKC
Receive
recovered
RSCT/RSCC
RSDT/RSDC
RSCT/RSCC
1
0
1
0
0
TPD0–TPD7
RSDT/RSDC
Receive
recovered
RSCT/RSCC
1
0
1
0
1
TPD0–TPD7
RSDT/RSDC
1
0
1
1
0
TPD0–TPD7
Receive
recovered
RSCT/RSCC
Receive
recovered
RSCT/RSCC
RSDT/RSDC
Receive
recovered
RSCT/RSCC
1
0
1
1
1
TPD0–TPD7
RSDT/RSDC
1
1
0
0
0
RSDT/RSDC
Receive
recovered
RSCT/RSCC
Receive
recovered
RSCT/RSCC
RSDT/RSDC
Receive
recovered
RSCT/RSCC
1
1
0
0
1
RSDT/RSDC
RSDT/RSDC
1
1
0
1
0
RSDT/RSDC
Receive
recovered
RSCT/RSCC
Receive
recovered
RSCT/RSCC
RSDT/RSDC
Receive
recovered
RSCT/RSCC
1
1
0
1
1
RSDT/RSDC
RSDT/RSDC
1
1
1
0
0
RSDT/RSDC
Receive
recovered
RSCT/RSCC
Receive
recovered
RSCT/RSCC
RSDT/RSDC
Receive
recovered
RSCT/RSCC
1
1
1
0
1
RSDT/RSDC
RSDT/RSDC
1
1
1
1
0
RSDT/RSDC
Receive
recovered
RSCT/RSCC
Receive
recovered
RSCT/RSCC
RSDT/RSDC
Receive
recovered
RSCT/RSCC
1
1
1
1
1
RSDT/RSDC
RSDT/RSDC
bit alignment
Figure 1 illustrates the bit-alignment function in the TNETA1610.
RSCT/RSCC
0
0
XX
XX (see Note B)
XX
XX
XX
XX
28 (first)
28
RSDT/RSDC
OOF
RPCK
RPD0–RPD7
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
First F6
Second F6
Twelfth F6
First 28
0
0
0
0
Second 28
See
Note A
NOTES: A. After the 12th contiguous F6 is detected, the bit alignment is adjusted so that the next eight bits (the first A2 byte) are grouped
together and sent out on RPD0–RPD7 after some delay time through the device.
B. Even when OOF is high, the TNETA1610 continues to convert the serial-input data to parallel-output data. While data is present
at the output, XX is shown to indicate that the alignment of the serial data into bytes on RPD0–RPD7 may not be known.
Figure 1. Bit Alignment
P
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