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TNETA1610
STS-12c/STM-4 RECEIVER/TRANSMITTER
WITH CLOCK RECOVERY/GENERATION
SDNS037 – SEPTEMBER 1995 – REVISED MARCH 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
transmit operation
The transmit parallel interface consists of TTL-compatible byte-wide input data (TPD0–TPD7), a
TTL-compatible transmit output clock (TPCK), and a TTL-compatible return clock input (RTNCK). TPCK is an
output to associated processing elements (i.e., a framer) that controls the output of byte-wide transmit data from
such devices. The return clock and data are input to the TNETA1610 such that byte-wide transmit data
(TPD0–TPD7) is clocked into the TNETA1610 on low-to-high transitions of RTNCK. If a return clock is not
available, RTNCK can be tied toTPCK provided the timing requirements between TPCK and TPD0–TPD7 can
be met.
The byte-wide data is converted to a 622.08-Mbit/s serial-data stream that is sent out differentially on transmit
serial-data true (TSDT) and transmit serial-data complement (TSDC). In addition, a phase-aligned 622.08-MHz
clock is sent out differentially on transmit serial-clock true (TSCT) and transmit serial-clock complement
(TSCC). The serial output data is valid on the rising edge of TSCT. TSDT, TSDC, TSCT, and TSCC are
pseudo-ECL-compatible outputs.
The transmit clock is generated from a 19.44-MHz input (TXREFCK) using an analog phase-lock loop. Two
other clock sources can be utilized as alternatives. If CKGENBP is at a high logic level, an external 622.08-MHz
clock is used. This clock is a differential input on pseudo-ECL-compatible terminals TXHCKT and TXHCKC. If
CKRECBP is at a low logic level and CLKLOOP or FLB is at a high logic level, the clock recovered from the
receive data stream is used for transmit operations. TXREFCK is used when CKGENBP, FLB, and CLKLOOP
are at a low logic level.
A facility-loopback (FLB) option is also available. When FLB is at a high logic level, the data input into the
receiver and the recovered clock are looped back to the transmitter outputs. This allows a method for loopback
testing of a system and for testing the clock-recovery function.
Transmit functions are reset by taking RESET low. This action can result in the loss of both transmit and receive
data.
receive operation
Serial data is provided to the TNETA1610 on true and complement, pseudo-ECL-compatible inputs RSDT and
RSDC. A phase-locked loop is used to recover the embedded clock from the serial-data stream. If the
clock-recovery function is bypassed (by setting CKRECBP to a high logic level), a 622.08-MHz
pseudo-ECL-compatible clock must be provided as a differential signal on RSCT and RSCC. The RSCT and
RSCC clock is not required if CKRECBP is at a low logic level.
The serial data is converted to byte-wide data and retimed to the recovered clock (or external clock if CKRECBP
is at a high logic level). The byte-wide output data (RPD0-RPD7) is valid on the rising edge of RPCK.
RPD0-RPD7 and RPCK are TTL-compatible outputs.
The TNETA1610 utilizes the out-of-frame (OOF) signal generated by subsequent processing elements for bit
alignment. When OOF goes high, the TNETA1610 begins searching the received data for a string of 12
consecutive A1 bytes (twelve hex F6s). Once this sequence is found, the TNETA1610 aligns the byte-wide data
output with the A1-byte boundaries so that subsequent data (i.e., the A2 bytes) is properly aligned. The
subsequent processing element (i.e., a framer) must detect and monitor the byte-aligned data for complete
SONET/SDH framing patterns (twelve A1s followed by twelve A2s) to ensure standards compliance for loss of
frame, etc. The TNETA1610 does not realign the output when OOF is low.
The TNETA1610 also performs a pseudo-ECL-to-TTL conversion of the loss-of-optical-carrier signal available
in many optical receivers. The TTL-compatible output (LOPC) goes high when the differential pseudo-ECL
inputs (FLAGT and FLAGC) go active, indicating an error condition. Thus, other components can avoid
pseudo-ECL circuitry by using the TNETA1610’s LOPC output. Furthermore, when a loss-of-optical-carrier
condition is detected, the processing of received data is interrupted such that receive data outputs
(RPD0–RPD7) are held low, and the output clock (RPCK) may drift from 622.08 MHz.
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