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參數(shù)資料
| 型號(hào)： | TNETA1610 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| 中文描述： | STS-12c/STM-4接收器/發(fā)射器的時(shí)鐘恢復(fù)/代（STS-12C/STM-4接收/傳送器） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 215K |
| 代理商： | TNETA1610 |
TNETA1610
STS-12c/STM-4 RECEIVER/TRANSMITTER
WITH CLOCK RECOVERY/GENERATION
SDNS037 – SEPTEMBER 1995 – REVISED MARCH 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
high-speed serial interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
RSCT, RSCC
I
(PECL)
Receive serial clock (true and complement). RSCT and RSCC are a differential
622.08-MHz clock that accompanies the incoming serial data on RSDT and RSDC
when CKRECBP is high.
RSDT, RSDC
I
(PECL)
Receive serial data (true and complement). RSDT and RSDC are differential data.
When CKRECBP is high, RSDT/RSDC is accompanied by clock RSCT/RSCC
such that RSDT/RSDC is valid on the rising edge of RSCT.
TSCT, TSCC
O
(PECL)
Transmit serial clock (true and complement). TSCT and TSCC are a differential,
phase-aligned 622.08-MHz clock.
TSDT, TSDC
O
(PECL)
Transmit serial data (true and complement). TSDT and TSDC are differential data
that is valid on the rising edge of TSCT.
TXHCKT, TXHCKC
I
(PECL)
Transmit high-speed clock (true and complement). TXHCKT and TXHCKC are a
differential 622.08-MHz clock source used when CKGENBP is high and CLKLOOP
and FLB are low.
control signals (see Table 1)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CKGENBP
I
(TTL)
Clock-generation bypass. When CKGENBP is low, the 622.08-MHz transmit clock
is generated from the 19.44-MHz clock on TXREFCK. When CKGENBP is high, a
622.08-MHz clock provided on TXHCKT/TXHCKC is used for transmit operations.
CKRECBP
I
(TTL)
Clock-recovery bypass. When CKRECBP is high, the 622.08-MHz clock on
RSCT/RSCC is used in the receiver. No clock is recovered from the data.
CLKLOOP
I
(TTL)
Transmit clock-source loop. When CLKLOOP is high, the clock used in the receive
data stream is also used for transmit operations.
FLB
I
(TTL)
Facility loopback. When FLB is high, the receive serial data and clock are looped
back to the transmit serial clock and data output.
OE
I
(TTL)
Output enable. OE enables or disables all TTL outputs. When OE is low, RPCK,
RPD0–RPD7, LOPC, and TPCK are placed in the high-impedance state. When OE
is high, these terminals function normally.
RESET
I
(TTL)
Reset. The TNETA1610 is reset by taking RESET low. This action can result in the
loss of transmit or receive data that is being processed.
TXREFCK
I
(TTL)
Transmit reference clock. TXREFCK is a 19.44-MHz clock that must be provided
if CKGENBP, CLKLOOP, and FLB are low.
P
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