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參數(shù)資料
| 型號： | TNETA1610 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| 中文描述： | STS-12c/STM-4接收器/發(fā)射器的時鐘恢復(fù)/代（STS-12C/STM-4接收/傳送器） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 215K |
| 代理商： | TNETA1610 |
TNETA1610
STS-12c/STM-4 RECEIVER/TRANSMITTER
WITH CLOCK RECOVERY/GENERATION
SDNS037 – SEPTEMBER 1995 – REVISED MARCH 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive operation (continued)
An output-enable (OE) terminal is provided to enable/disable all TTL outputs. When OE is low, RPCK,
RPD0–RPD7, LOPC, and TPCK are held in the high-impedance state. When OE is high, these terminals
function as previously described.
Receive functions are reset by taking RESET low. This action can result in the loss of any data being processed.
data/clock source control
There are five control inputs to the TNETA1610 that change the source of data (and/or clock) for a given output.
The effects of these inputs (OE, FLB, CLKLOOP, CKGENBP, and CKRECBP) are indicated in Table 1.
Table 1. Data/Clock Source Control
STATE OF INPUTS
CLKLOOP
SOURCE OF DATA/CLOCK FOR OUTPUTS
TSCT/TSCC
TPCK
High
impedance
High
impedance
TXHCKT/
TXHCKC
impedance
TXHCKT/
TXHCKC
impedance
Receive
recovered
impedance
High
impedance
Receive
recovered
impedance
High
impedance
Receive
recovered
impedance
High
impedance
Receive
recovered
impedance
High
impedance
Receive
recovered
impedance
High
impedance
Receive
recovered
impedance
High
impedance
OE
FLB
CKGENBP
CKRECBP
TSDT/TSDC
RPD0-RPD7
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
RPCK
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
Receive
recovered
RSCT/RSCC
Receive
recovered
0
0
0
0
0
N/A
TXREFCK
0
0
0
0
1
N/A
TXREFCK
0
0
0
1
0
N/A
High
0
0
0
1
1
N/A
High
0
0
1
0
0
N/A
High
0
0
1
0
1
N/A
RSCT/RSCC
0
0
1
1
0
N/A
High
0
0
1
1
1
N/A
RSCT/RSCC
0
1
0
0
0
RSDT/RSDC
High
0
1
0
0
1
RSDT/RSDC
RSCT/RSCC
0
1
0
1
0
RSDT/RSDC
High
0
1
0
1
1
RSDT/RSDC
RSCT/RSCC
0
1
1
0
0
RSDT/RSDC
High
0
1
1
0
1
RSDT/RSDC
RSCT/RSCC
0
1
1
1
0
RSDT/RSDC
High
0
1
1
1
1
RSDT/RSDC
RSCT/RSCC
1
0
0
0
0
TPD0-TPD7
TXREFCK
TXREFCK
RSDT/RSDC
1
0
0
0
1
TPD0–TPD7
TXREFCK
TXHCKT/
TXHCKC
TXREFCK
TXHCKT/
TXHCKC
RSDT/RSDC
1
0
0
1
0
TPD0–TPD7
RSDT/RSDC
This is not a normal operating condition. As no clock is output on TPCK, valid data cannot be properly input on TPD0–TPD7. Thus, data output
on TSDT/TSDC may be invalid.
P
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