td(IDLEXCOL) Wake-up Signal (H) X1/X2 or XCLKIN XCLKOUT Flushing Pipeline (A) Device Status STANDBY Nor" />
參數(shù)資料
型號: TMX320F28069UPZPA
廠商: Texas Instruments
文件頁數(shù): 60/174頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLSH 100HTQFP
產(chǎn)品培訓模塊: ControlSUITE
Piccolo F2806x
TPS75005 Single IC Power for C2000 MCU
標準包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 50K x 16
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP 裸露焊盤
包裝: 托盤
其它名稱: 296-30086
TMX320F28069UPZPA-ND
td(IDLEXCOL)
Wake-up
Signal
(H)
X1/X2 or
XCLKIN
XCLKOUT
Flushing Pipeline
(A)
Device
Status
STANDBY
Normal Execution
STANDBY
(G)
(B)
(C)
(D)(E)
(F)
tw(WAKE-INT)
td(WAKE-STBY)
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
A.
IDLE instruction is executed to put the device into STANDBY mode.
B.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D.
The external wake-up signal is driven active.
E.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F.
After a latency period, the STANDBY mode is exited.
G.
Normal execution resumes. The device will respond to the interrupt (if enabled).
H.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-55. STANDBY Entry and Exit Timing Diagram
Table 5-74. HALT Mode Timing Requirements
MIN
MAX
UNIT
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
toscst + 2tc(OSCCLK)
cycles
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
toscst + 8tc(OSCCLK)
cycles
Table 5-75. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low
32tc(SCO)
45tc(SCO)
cycles
tp
PLL lock-up time
1
ms
Delay time, PLL lock to program execution resume
1125tc(SCO)
cycles
Wake up from flash
td(WAKE-HALT)
Flash module in sleep state
35tc(SCO)
cycles
Wake up from SARAM
152
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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