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SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
1
TMS570LS Series 16/32-BIT RISC Flash
5.2
Die-ID Registers
....................................
59Microcontroller
.......................................... 1 5.3
PLL Registers
.......................................
601.1
Features
..............................................
16
Device Electrical Specifications
1.2
Description
...........................................
26.1
Operating Conditions
...............................
611.3
Functional Block Diagram
............................
56.2
Absolute Maximum Ratings Over Operating
Free-Air Temperature Range (unless otherwise
1.4
Terms and Acronyms
................................
6noted)
...............................................
612
Device Overview
........................................ 8 6.3
Device Recommended Operating Conditions
2.1
Device Characteristics
...............................
86.4
Electrical Characteristics Over Operating Free-Air
2.2
Memory
..............................................
9Temperature Range
................................
622.3
Pin Assignments
....................................
177
Peripheral and Electrical Specifications
2.4
Terminal Functions
.................................
227.1
Clocks
..............................................
662.5
Device Support
.....................................
357.2
ECLK Specification
.................................
703
Reset / Abort Sources
................................ 37 7.3
RST And PORRST Timings
........................
713.1
Reset / Abort Sources
..............................
377.4
TEST Pin Timing
...................................
734
Peripherals
.............................................. 40 7.5
DAP - JTAG Scan Interface Timing
4.1
Error Signaling Module (ESM)
......................
407.6
Output Timings
.....................................
754.2
Direct Memory Access (DMA)
......................
437.7
Input Timings
.......................................
764.3
High End Timer Transfer Unit (HET-TU)
7.8
Flash Timings
.......................................
777.9
SPI Master Mode Timing Parameters
4.4
Vectored Interrupt Manager (VIM)
7.10
SPI Slave Mode Timing Parameters
4.5
MIBADC Event Trigger Sources
7.11
CAN Controller Mode Timings
......................
864.6
MIBSPI
..............................................
487.12
SCI/LIN Mode Timings
.............................
864.7
ETM
.................................................
507.13
FlexRay Controller Mode Timings
4.8
Debug Scan Chains
................................
517.14
EMIF Timings
.......................................
874.9
CCM
................................................
527.15
ETM Timings
.......................................
894.10
LPM
.................................................
537.16
RTP Timings
........................................
914.11
Voltage Monitor
.....................................
537.17
DMM Timings
.......................................
934.12
CRC
................................................
537.18
MibADC
.............................................
944.13
System Module Access
.............................
538
Revision History
...................................... 100 4.14
Debug ROM
........................................
549
Mechanical Packaging and Orderable
Information
............................................ 101 4.15
CPU Self Test Controller: STC / LBIST
9.1
Thermal Data
......................................
1015
Device Registers
....................................... 57 9.2
Packaging Information
............................
1015.1
Device Identification Code Register
Copyright 2010–2011, Texas Instruments Incorporated
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