參數(shù)資料
型號: TMS570LS10216ASZWTQR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337
封裝: GERRN, PLASTIC, NFBGA-337
文件頁數(shù): 23/102頁
文件大?。?/td> 1146K
代理商: TMS570LS10216ASZWTQR
PRODUCTPREVIEW
www.ti.com
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
Table 2-8. Terminal Functions (continued)
Terminal
Internal
TMS570LSXXX16
TMS570LSXXX06
Type
pullup/p
Description
Name
ulldown
337
144
337
144
System Module (SYS)
Power on Reset Pin. External power
IPD
PORRST
W7
28
W7
28
3.3V I
supply monitor circuitry must assert a
(100A)
power-on reset on this pin.
Active Low Bidirectional Reset pin. An
external device can assert a device reset
on this pin.
The output buffer on this pin is
IPU
implemented as an open drain (drives
RST
B17
85
B17
85
4mA
(100A)
low only).
3.3V I/O
To ensure an external reset is not
arbitrarily generated, TI recommends
that an external pullup resistor is
connected to this pin.
IPD
External Clock Prescaler module output
ECLK
A12
88
A12
88
8mA
(20A)
pin or GIO pin
Tset/Debug (T/D)
IPD
JTAG test clock pin. Clocks the JTAG
TCK
B18
30
B18
30
3.3V I
(100uA)
debug logic.
RTCK
A16
35
A16
35
3.3V O
JTAG return test clock pin. (JTAG)
IPU
TDI
A17
34
A17
34
JTAG test data in pin.
(100uA)
IPD
8 mA
TDO
C18
33
C18
33
JTAG test data out pin.
3.3V I/O
(100uA)
JTAG serial input pin for controlling the
IPU
TMS
C19
36
C19
36
state of the CPU test access port (TAP)
(100uA)
controller.
JTAG test hardware reset to TAP. IEEE
IPD
TRST
D18
29
D18
29
Standard 1149-1 (JTAG) Boundary-Scan
(100uA)
Logic
3.3V I
Test enable pin. Reserved for internal TI
IPD
use only. For proper operation, this pin
TEST
U2
58
U2
58
(100uA)
must be connected to ground, e.g. using
a external resistor.
Error Signaling Module (ESM)
IPD
ERROR
B14
143
B14
143
3.3V I/O
8mA
Error Signaling pin
(20uA)
Flash
Flash Test Pad 1 pin. For proper
operation this pin must connect only to a
test pad or not be connected at all [no
FLTP1
J5
122
J5
122
connect (NC)]. The test pad must not be
exposed in the final product where it
might be subjected to an ESD event.
Flash Test Pad 2 pin. For proper
operation this pin must connect only to a
test pad or not be connected at all [no
FLTP2
H5
123
H5
123
connect (NC)]. The test pad must not be
exposed in the final product where it
might be subjected to an ESD event.
Flash pump voltage supply (3.3 V). This
3.3V
VCCP
F8
128
F8
128
pin is required for Flash read, program
PWR
and erase operations.
Copyright 2010–2011, Texas Instruments Incorporated
Device Overview
27
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