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參數(shù)資料
| 型號(hào)： | TMS570LS10216ASZWTQR |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337 |
| 封裝： | GERRN, PLASTIC, NFBGA-337 |
| 文件頁(yè)數(shù)： | 54/102頁(yè) |
| 文件大小： | 1146K |
| 代理商： | TMS570LS10216ASZWTQR |
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PRODUCTPREVIEW
www.ti.com
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
4.15 CPU Self Test Controller: STC / LBIST
The CPU Self Test Controller (STC) is used to test the ARM CPU core using a Deterministic Logic BIST
(LBIST) Controller as the test engine. The STC has the capability of dividing the complete test run into
smaller independent test sets (intervals). The test coverage and number of test execution cycles for each
test interval is shown in the table below.
The maximum clock rate for the STC / LBIST is:
53.333MHz when HCLK = 160MHz / VCLK = 80MHz on BGA package
50MHz when HCLK = 100MHz / VCLK = 100MHz on QFP and BGA packages
46.666MHz when HCLK = 140MHz / VCLK = 70MHz on QFP and BGA packages
In order to achieve the proper clock rate during CPU self test a STC clock divider has been implemented.
The clock divider is set by the CLKDIV bits in STCCLKDIV register in the secondary system module frame
at location 0xFFFF E108. The default value of the CPU Self Test LBIST clock divider is set to 'divide-by-1’.
NOTE
The supply current while performing CPU self test is different than the device operating
Table 4-16. STC/LBIST Test Coverage and Duration
Intervals
Test Coverage
Test Cycles (STC Clock Cycles)
0
0%
0
1
57.14%
1,555
2
65.82%
3,108
3
70.56%
4,661
4
73.56%
6,214
5
76.06%
7,767
6
78.07%
9,320
7
79.62%
10,873
8
80.92%
12,426
9
82.1%
13,979
10
82.94%
15,532
11
83.76%
17,085
12
84.51%
18,638
13
85.12%
20,191
14
85.62%
21,744
15
86.19%
23,297
16
86.56%
24,850
17
86.97%
26,403
18
87.33%
27,956
19
87.67%
29,509
20
88.01%
31,062
21
88.31%
32,615
22
88.58%
34,168
23
88.87%
35,721
24
89.11%
37,274
25
89.34%
38,827
26
89.59%
40,380
27
89.82%
41,933
28
90.05%
43,486
Copyright 2010–2011, Texas Instruments Incorporated
Peripherals
55
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