參數(shù)資料
型號(hào)： TMS320LC545A-66
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 50/132頁
文件大?。?/td> 1707K
代理商： TMS320LC545A-66
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PWM characteristics
Characteristics of the PWMs are as follows:
16-bit registers
Programmable deadband for the PWM output pairs, from 0 to 12
μ
s
Minimum deadband width of 25 ns
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and
after
PDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
–
PDPINTA pin status is reflected in bit 8 of COMCONA register.
–
PDPINTB pin status is reflected in bit 8 of COMCONB register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
Capture units include the following features:
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)
—
one input pin per capture unit. [All inputs
are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold
at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also
be used as QEP inputs to the QEP circuit.]
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
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