參數(shù)資料
型號： TMS320LC545A-66
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 112/132頁
文件大?。?/td> 1707K
代理商： TMS320LC545A-66
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
112
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
Flash parameters @40 MHz CLOCKOUT
PARAMETER
Time/Word (16-bit)
MIN
TYP
30
MAX
UNIT
μ
s
ms
Clear/Programming time
Time/4K Sector
130
Time/12K Sector
400
ms
Erase time
Time/4K Sector
350
ms
Time/12K Sector
1
s
ICCP (VCCP pin current)
Indicates the typical/maximum current consumption during the
Clear-Erase-Program (C-E-P) cycle
5
15
mA
TI releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change.
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when VDD = 3.3 V and VCCP = 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance
could also impact the timing parameters.
migrating from LF240xA (Flash) devices to LC240xA (ROM) devices
Table 18 outlines the differences between the LF240xA (Flash) devices and the LC240xA (ROM) devices.
These differences should be taken into consideration when migrating between the devices.
Table 18. Differences Between LF240xA (Flash) Devices and LC240xA (ROM) Devices
FEATURE
LF2406A
32K
LC2406A
32K
LC2404A
16K
LF2403A
16K
LF2402A
8K
LC2402A
6K
On-chip Flash or ROM
Single-Access RAM (SARAM)
(16-bit words)
2K
2K
1K
512
512
—
Boot ROM
Yes
—
—
Yes
Yes
—
Event Managers
EVA, EVB
EVA, EVB
EVA, EVB
EVA
EVA
EVA
ADC Channels
16
16
16
8
8
8
SPI
Yes
Yes
Yes
Yes
§
—
—
CAN
Yes
Yes
—
Yes
—
—
GPIO Pins
41
41
41
21
21
21
BIO Pin
Yes
Yes
Yes
—
—
—
TDIRx Pin
Yes
Yes
Yes
—
—
—
External Interrupts
5
5
5
3
3
3
Access to External Memory Spaces
(NOTE: Application code should
NOT
access Illegal/Reserved
addresses.)
See Note 2
See Note 3
See Note 3
See Note 2
See Note 2
See Note 3
VCCP Pin Functionality
VCCP
100-pin
PZ
No Connect
No Connect
VCCP
64-pin
PAG
VCCP
64-pin
PG
No Connect
Packaging
100-pin
PZ
100-pin
PZ
64-pin
PG, PAG
§
The SPISTE pin is not available on the LF2403A. See the SPI Slave Mode Operation in LF2403A section.
NOTES:
2. Access to external Program, Data, and I/O space is considered illegal and would assert an NMI.
3. The external Program and I/O spaces are implemented as
“
reserved
”
addresses and any access will not assert an NMI. However,
the external data memory space is illegal.
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