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| 型號(hào)： | TMS320LC545A-66 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 38/132頁(yè) |
| 文件大小： | 1707K |
| 代理商： | TMS320LC545A-66 |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
240xA legend for the internal hardware
Table 4. Legend for the 240xA DSP CPU Internal Hardware
SYMBOL
NAME
DESCRIPTION
ACC
Accumulator
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities
ARAU
Auxiliary Register
Arithmetic Unit
An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs
AUX
REGS
Auxiliary Registers
0
–
7
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
C
Carry
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
CALU
Central Arithmetic
Logic Unit
32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.
DARAM
Dual-Access RAM
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 0300
–
03FF and 0060
–
007F, respectively. Blocks 0
and 1 contain 256 words, while block 2 contains 32 words.
DP
Data Memory
Page Pointer
The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to
form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.
GREG
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space. Since the global memory space is not used in
the 240xA devices, this register is reserved.
IMR
Interrupt Mask
Register
IMR individually masks or enables the seven interrupts.
IFR
Interrupt Flag
Register
The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable
interrupts.
INT#
Interrupt Traps
A total of 32 interrupts by way of hardware and/or software are available.
ISCALE
Input Data-Scaling
Shifter
16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
MPY
Multiplier
16
×
16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MSTACK
Micro Stack
MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
MUX
Multiplexer
Multiplexes buses to a common input
NPAR
Next Program
Address Register
NPAR holds the program address to be driven out on the PAB in the next cycle.
OSCALE
Output
Data-Scaling
Shifter
16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data
bus (DWEB).
PAR
Program Address
Register
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PC
Program Counter
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PCTRL
Program
Controller
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
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