參數(shù)資料
型號： TMS320LC545A-66
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 17/132頁
文件大小： 1707K
代理商： TMS320LC545A-66
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)
CANRX
70
49
–
IOPC7
70
49
49
CANRX/
IOPC7
63
CAN receive data or GPIO (LF2403A)
(
↑
)
63
GPIO only (2402A)
(
↑
)
CANTX/
IOPC6
CANTX
72
50
–
64
CAN transmit data or GPIO (LF2403A)
(
↑
)
IOPC6
72
50
50
64
GPIO only (2402A)
(
↑
)
SCITXD/
IOPA0
25
17
17
43
SCI asynchronous serial port transmit data or GPIO
(
↑
)
SCIRXD/
IOPA1
26
18
18
44
SCI asynchronous serial port receive data or or
GPIO
(
↑
)
SPICLK/
IOPC4
SPICLK
35
24
24
47
SPI clock or GPIO (LF2403A)
(
↑
)
IOPC4
35
24
24
47
GPIO only (2402A)
(
↑
)
SPISIMO/
IOPC2
SPISIMO
30
21
21
45
SPI slave in, master out or GPIO (LF2403A)
(
↑
)
SPI slave out, master in or GPIO (LF2403A)
(
↑
)
(
↑
)
IOPC2
30
21
21
45
GPIO only (2402A)
SPISOMI/
IOPC3
SPISOMI
32
22
22
46
(
↑
)
IOPC3
32
22
22
46
GPIO only (2402A)
SPISTE/
IOPC5
SPISTE
33
23
23
–
SPI slave transmit enable (optional) or GPIO
SPI slave transmit-enable (optional) or GPIO
(
↑
)
IOPC5
33
23
23
–
EXTERNAL INTERRUPTS, CLOCK
RS
133
93
93
28
Device reset. RS causes the 240xA to terminate execution
and sets PC = 0. When RS is brought to a high level,
execution begins at location zero of program memory. RS
affects (or sets to zero) various registers and status bits.
When the watchdog timer overflows, it initiates a system
reset pulse that is reflected on the RS pin.
(
↑
)
PDPINTA
7
6
6
36
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVA) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTA is a falling-edge-sensitive interrupt.
(
↑
)
XINT1/
IOPA2
23
16
16
External user interrupt 1 or GPIO. Both XINT1 and XINT2
are
edge-sensitive.
The
programmable.
(
↑
)
External user interrupt 2 and ADC start of conversion or
GPIO. External
“
start-of-conversion
”
input for ADC/GPIO.
Both XINT1 and XINT2 are edge-sensitive. The edge
polarity is programmable.
(
↑
)
edge
polarity
is
XINT2/ADCSOC/
IOPD0
21
15
15
42
Bold, italicized pin names
indicate pin function after reset.
GPIO
–
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
–
Internal pullup
↓
–
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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