參數(shù)資料
型號： TMS320LC541-66
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 97/111頁
文件大?。?/td> 1426K
代理商： TMS320LC541-66
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
97
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial-port receive timing in TDM mode
timing requirements for serial-port receive in TDM mode [H = 0.5t
c(CO)
] (’542/’543 only)
(see Figure 38)
’542
’543
UNIT
MIN
MAX
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(TD-TCL)
th(TCH-TD)
th(TCL-TD)
tsu(TF-TCH)
th(TCH-TF)
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching nfinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 39.
Cycle time, serial-port clock
8H
ns
Fall time, serial-port clock
6
ns
Rise time, serial-port clock
6
ns
Pulse duration, serial-port clock low/high
4H
ns
Setup time, TDAT/TADD before TCLK falling edge
–(3H–9)
ns
Hold time, TDAT/TADD after TCLK rising edge, tw(SCKL) < 5H
Hold time, TDAT/TADD after TCLK falling edge, tw(SCKL) > 5H
Setup time, TFRM before TCLK rising edge
0
ns
5H+5
ns
10
ns
Hold time, TFRM after TCLK rising edge
10
ns
timing requirements for serial-port receive in TDM mode [H = 0.5t
c(CO)
] (’54x devices other than
’542/’543) (see Figure 38)
’C54x-40
’LC54x-40
’LC54x-50
’54X-66
UNIT
MIN
MAX
MIN
MAX
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(TD-TCH)
th(TCH-TD)
tsu(TF-TCH)
th(TCH-TF)
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching nfinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 39.
Cycle time, serial-port clock
8H
16H
ns
Fall time, serial-port clock
6
6
ns
Rise time, serial-port clock
6
6
ns
Pulse duration, serial-port clock low/high
4H
8H
ns
Setup time, TDAT/TADD before TCLK rising edge
25
10
ns
Hold time, TDAT/TADD after TCLK rising edge
– 6
1
ns
Setup time, TFRM before TCLK rising edge
10
10
ns
Hold time, TFRM after TCLK rising edge
10
10
ns
相關PDF資料
PDF描述
TMS320LC542-40 Digital Signal Processor
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相關代理商/技術參數(shù)
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TMS320LC541PZ1-40 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320LC541PZ2-40 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320LC542PBK1-50 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320LC542PBK2-50 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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