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| 型號： | TMS320F240PQS |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 20/105頁 |
| 文件大?。?/td> | 1481K |
| 代理商： | TMS320F240PQS |
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TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reset (continued)
The occurrence of a reset condition causes the TMS320x240 to terminate program execution and affects
various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are
affected by a reset are initialized to their reset state. In the case of a power-on reset, the PLL control registers
are initialized to zero. The program needs to recognize power-on resets and configure the PLL for correct
operation.
After a reset, the program can check the power-on reset flag (PORST flag, SYSSR.15), the illegal address flag
(ILLADR flag, SYSSR.12), the software reset flag (SWRST flag, SYSSR.10), and the watchdog reset flag
(WDRST flag, SYSSR.9) to determine the source of the reset. A reset does not clear these flags.
RS and PORESET must be held low until the clock signal is valid and V
CC
is within the operating range. In
addition, PORESET must be driven low when V
CC
drops below the minimum operating voltage.
hardware-generated interrupts
All the hardware interrupt lines of the DSP core are given a priority rank from 1 to 10 (1 being highest). When
more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets
acknowledged first. The others are acknowledged in order after that. Of those ten lines, six are for maskable
interrupt lines (INT1–INT6) and one is for the nonmaskable interrupt (NMI) line. INT1–INT6 and NMI have the
priorities shown in Table 5.
Table 5. Interrupt Priorities at the Level of the DSP Core
INTERRUPT
PRIORITY AT THE
DSP CORE
RESET
1
TI RESERVED
2
NMI
3
INT1
4
INT2
5
INT3
6
INT4
7
INT5
8
INT6
9
TI RESERVED
TI Reserved means that the address space is
reserved for Texas Instruments.
10
The inputs to these lines are controlled by the system module and the event manager as summarized in Table 6
and shown in Figure 5.
Table 6. Interrupt Lines Controlled by the System Module and Event Manager
PERIPHERAL
INTERRUPT LINES
System Module
INT1
INT5
INT6
NMI
Event Manager
INT2
INT3
INT4
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|---|---|
| TMS320F241FN | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F241FN | 制造商:Texas Instruments 功能描述:IC C2000 DSP SMD 320F241 PLCC68 |
| TMS320F241FNA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F241FNS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F241PG | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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