參數(shù)資料
型號(hào)： TMS320F240PQS
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 18/105頁(yè)
文件大?。?/td> 1481K
代理商： TMS320F240PQS
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description of group2 shared I/O pins
Group2 shared pins belong to peripherals that have built-in general-purpose I/O capability. Control and
configuration for these pins are achieved by setting the appropriate bits within the control and configuration
registers of the peripherals. Table 3 lists the Group2 shared pins.
Table 3. Group2 Shared Pin Configurations
PIN #
PRIMARY FUNCTION
REGISTER
ADDRESS
PERIPHERAL MODULE
43
SCIRXD
SCIPC2
705Eh
SCI
44
SCITXD
SCIPC2
705Eh
SCI
45
SPISIMO
SPIPC2
704Eh
SPI
48
SPISOMI
SPIPC2
704Eh
SPI
49
SPICLK
SPIPC1
704Dh
SPI
51
SPISTE
SPIPC1
704Dh
SPI
54
XINT2
XINT2CR
7078h
External Interrupts
55
XINT3
XINT3CR
707Ah
External Interrupts
digital I/O control registers
Table 4 lists the registers available to the digital I/O module. As with other ’x240 peripherals, the registers are
memory-mapped to the data space.
Table 4. Addresses of Digital I/O Control Registers
ADDRESS
REGISTER
NAME
7090h
OCRA
I/O mux control register A
7092h
OCRB
I/O mux control register B
7098h
PADATDIR
I/O port A data and direction register
709Ah
PBDATDIR
I/O port B data and direction register
709Ch
PCDATDIR
I/O port C data and direction register
device reset and interrupts
The TMS320x240 software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The ’x240 recognizes three types of
interrupt sources:
Reset
(hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
Hardware-generated interrupts
are requested by external pins or by on-chip peripherals. There are two
types:
–
External interruptsare generated by one of five external pins corresponding to the interrupts XINT1,
XINT2, XINT3, PDPINT, and NMI. The first four can be masked both by dedicated enable bits and by the
CPU’s interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI,
which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can
be locked out only by an already executing NMI or a reset.
–
Peripheral interrupts
are initiated internally by these on-chip peripheral modules: the event manager,
SPI, SCI, watchdog/real-time interrupt (WD/RTI), and ADC. They can be masked both by enable bits
for each event in each peripheral and by the CPU’s IMR, which can mask each maskable interrupt line at
the DSP core.
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