參數(shù)資料
型號(hào)： TMS320F240PQQ
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁數(shù)： 66/105頁
文件大?。?/td> 1481K
代理商： TMS320F240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
66
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CLOCK OPTIONS
clock options
PARAMETER
CLKMD[1:0]
Clock-in mode, divide-by-2
00
Clock-in mode, divide-by-1
01
PLL enabled, divide-by-2 before PLL lock
10
PLL enabled, divide-by-1 before PLL lock
11
timings with the PLL circuit disabled
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
fx
fx
Input clock frequency, divide-by-2 mode
TA = –40
°
C to 125
°
C
TA = –40
°
C to 125
°
C
0
0
40
MHz
Input clock frequency, divide-by-1 mode
This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
20
MHz
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
]
(see Note 1 and Figure 21)
PARAMETER
CLOCK MODE
MIN
TYP
MAX
UNIT
t(CPU)
tc(CPU)
Cycle time CPUCLK
Cycle time, CPUCLK
CLKIN divide by 2
2tc(Cl)
tc(Cl)
2tc(CPU)
4tc(CPU)
2tc(Cl)
tc(Cl)
ns
CLKIN divide by 1
t(SYS)
tc(SYS)
Cycle time SYSCLK
Cycle time, SYSCLK
CPUCLK divide by 2
CPUCLK divide by 4
ns
t(CO)
tc(CO)
Cycle time CLKOUT
Cycle time, CLKOUT
CLKIN divide by 2
ns
CLKIN divide by 1
td(CIH-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
SYSCLK is initialized to divide-by-4 mode by any device reset.
NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
Delay time, XTAL1/CLKIN high to CLKOUT high/low
3
18
32
ns
Fall time, CLKOUT
5
ns
Rise time, CLKOUT
5
ns
Pulse duration, CLKOUT low
H–10
H–6
H–1
ns
Pulse duration, CLKOUT high
H+0
H+4
H+8
ns
timing requirements over recommended operating conditions (see Figure 21)
CLOCK-IN MODE
Divide by 2
MIN
MAX
UNIT
t(Cl)
tc(Cl)
Cycle time XTAL1/CLKIN
Cycle time, XTAL1/CLKIN
25
ns
Divide by 1
50
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
Fall time, XTAL1/CLKIN
5
ns
Rise time, XTAL1/CLKIN
5
ns
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
45
55
%
45
55
%
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