參數(shù)資料
型號: TMS320F240PQQ
英文描述: 16-Bit Microcontroller
中文描述: 16位微控制器
文件頁數(shù): 47/105頁
文件大?。?/td> 1481K
代理商: TMS320F240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial communications interface (SCI) module
The TMS320x240 devices include a serial communications interface (SCI) module. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate (baud) is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
Two external pins
SCITXD: SCI transmit-output pin or general-purpose bidirectional I/O pin
SCIRXD: SCI receive-input pin or general-purpose bidirectional I/O pin
Baud rate programmable to 64K different rates
Up to 625 Kbps at 10-MHz SYSCLK
Data word format
One start bit
Data word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non return-to-zero) format
Eleven SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are interfaced to the 16-bit peripheral bus. When a register is accessed, the register
data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
Figure 14 shows the SCI module block diagram.
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