參數(shù)資料
型號(hào)： TMS320F240PQQ
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 40/105頁(yè)
文件大?。?/td> 1481K
代理商： TMS320F240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external memory interface (continued)
The bus request (BR) signal is used in conjunction with the other ’x240 interface signals to arbitrate external
global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted
at the beginning of the access. When an external global-memory device receives the bus request, it responds
by asserting the ready signal after the global-memory access is arbitrated and the global access is completed.
The TMS320x240 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the ’x240 to buffer the transition of the data bus from input to output (or output
to input) by a half cycle. In most systems, TMS320x240 ratio of reads to writes is significantly large to minimize
the overhead of the extra cycle on writes.
Wait states can be generated when accessing slower external resources. The wait states operate on
machine-cycle boundaries and are initiated either by using the ready signal or using the software wait-state
generator. Ready can be used to generate any number of wait states.
event-manager (EV) module
The event-manager module includes general-purpose (GP) timers, full compare units, capture units, and
quadrature-encoder pulse (QEP) circuits. Figure 11 shows the functions of the event manager.
general-purpose (GP) timers
There are three GP timers on the TMS320x240. The GP timer x (for x = 1, 2, 3) includes:
A 16-bit timer up-, up/down-counter, TxCNT for reads or writes
A 16-bit timer-compare register (double-buffered with shadow register), TxCMPR for reads or writes
A 16-bit timer-period register (double-buffered with shadow register), TxPR for reads or writes
A 16-bit timer-control register,TxCON for reads or writes
Selectable internal or external input clocks
A programmable prescalar for internal or external clock inputs
Control and interrupt logic for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
A timer-compare output pin with configurable active-low and active-high states, as well as forced-low and
forced-high states.
A selectable direction (TMRDIR) input pin (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. A 32-bit GP timer also can be
configured using GP timer 2 and 3. The compare register associated with each GP timer can be used for
compare function and PWM-waveform generation. There are two single and three continuous modes of
operation for each GP timer in up- or up/down-counting operations. Internal or external input clocks with
programmable prescaler is used for each GP timer. The state of each GP timer/compare output is configurable
by the general-purpose timer-control register (GPTCON). GP timers also provide the time base for the other
event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 1 or 2 for the simple
compares to generate additional compare or PWMs, GP timer 2 or 3 for the capture units and the
quadrature-pulse counting operations.
Double buffering of the period and compare registers allows programmable change of the timer (PWM) period
and the compare/PWM pulse width as needed.
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TMS320F241FNS 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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