參數(shù)資料
型號(hào)： TMS320C82GGP-60
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-Bit Digital Signal Processor
中文描述： 32位數(shù)字信號(hào)處理器
文件頁數(shù)： 99/132頁
文件大?。?/td> 1707K
代理商： TMS320C82GGP-60
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
99
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
SPI slave mode external timing parameters (clock phase = 1)
(see Figure 43)
NO.
12
MIN
MAX
UNIT
ns
tc(SPC)S
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
Cycle time, SPICLK
8tc(CO)
0.5tc(SPC)S
–
10
0.5tc(SPC)S
–
10
0.5tc(SPC)S
–
10
0.5tc(SPC)S
–
10
0.125tc(SPC)S
0.125tc(SPC)S
13
§
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
14
§
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
17
§
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
ns
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
18
§
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0.75tc(SPC)S
ns
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75tc(SPC)S
21
§
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
ns
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
22
§
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
ns
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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