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參數(shù)資料
| 型號： | TMS320C82GGP-60 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-Bit Digital Signal Processor |
| 中文描述： | 32位數(shù)字信號處理器 |
| 文件頁數(shù)： | 63/132頁 |
| 文件大小： | 1707K |
| 代理商： | TMS320C82GGP-60 |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
digital I/O and shared pin functions
The 240xA has up to 41 general-purpose, bidirectional, digital I/O (GPIO) pins
—
most of which are shared
between primary functions and I/O. Most I/O pins of the 240xA are shared with other functions. The digital I/O
ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and
shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
Output Control Registers
—
used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
Data and Control Registers
—
used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
The control structure for shared I/O pins is shown in Figure 17, where each pin has three bits that define its
operation:
Mux control bit
—
this bit selects between the primary function (1) and I/O function (0) of the pin.
I/O direction bit
—
if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
I/O data bit
—
if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
Pin
(Read/Write)
IOP Data Bit
In
Out
0 = Input
1 = Output
0
1
MUX Control Bit
0 = I/O Function
1 = Primary Function
IOP DIR Bit
Primary
Function
or I/O Pin
Pullup
or
Pulldown
(Internal)
Primary
Function
(Output Section)
Primary
Function
(Input Section)
Figure 17. Shared Pin Configuration
A summary of shared pin configurations and associated bits is shown in Table 12.
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