參數(shù)資料
型號： TMS320C82GGP-60
元件分類： 數(shù)字信號處理
英文描述： 32-Bit Digital Signal Processor
中文描述： 32位數(shù)字信號處理器
文件頁數(shù)： 64/132頁
文件大?。?/td> 1707K
代理商： TMS320C82GGP-60
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
64
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
description of shared I/O pins (continued)
Table 12. Shared Pin Configurations
PIN FUNCTION SELECTED
MUX
CONTROL
REGISTER
(name.bit #)
MUX CONTROL
VALUE AT RESET
(MCRx.n)
I/O PORT DATA AND DIRECTION
(MCRx.n = 1)
Primary Function
(MCRX.N = 0)
I/O
REGISTER
DATA BIT NO.
§
DIR BIT NO.
PORT A
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PORT B
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PORT C
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PORT D
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
SCITXD
SCIRXD
XINT1
CAP1/QEP1
CAP2/QEP2
CAP3
PWM1
PWM2
IOPA0
IOPA1
IOPA2
IOPA3
IOPA4
IOPA5
IOPA6
IOPA7
MCRA.0
MCRA.1
MCRA.2
MCRA.3
MCRA.4
MCRA.5
MCRA.6
MCRA.7
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PWM3
PWM4
PWM5
PWM6
IOPB0
IOPB1
IOPB2
IOPB3
IOPB4
IOPB5
IOPB6
IOPB7
MCRA.8
MCRA.9
MCRA.10
MCRA.11
MCRA.12
MCRA.13
MCRA.14
MCRA.15
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T1PWM/T1CMP
T2PWM/T2CMP
TDIRA
TCLKINA
W/R
#
BIO
SPISIMO
SPISOMI
SPICLK
SPISTE
CANTX
CANRX
IOPC0
IOPC1
IOPC2
IOPC3
IOPC4
IOPC5
IOPC6
IOPC7
MCRB.0
MCRB.1
MCRB.2
MCRB.3
MCRB.4
MCRB.5
MCRB.6
MCRB.7
1
1
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XINT2/ADCSOC
EMU0
EMU1
TCK
TDI
TDO
TMS
TMS2
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
§
If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
#At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A),
W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)
is reserved in these devices and must be written with a zero.
||Note that bits 15 through 9 of the MCRB register
must
be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation
of the device.
IOPD0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MCRB.8
MCRB.9||
MCRB.10||
MCRB.11||
MCRB.12||
MCRB.13||
MCRB.14||
MCRB.15||
0
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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