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TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
98
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
REG
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PLL CLOCK CONTROL REGISTERS (CONTINUED)
0702Dh
CKINF(3)
CKINF(2)
CKINF(1)
CKINF(0)
PLLDIV(2)
PLLFB(2)
PLLFB(1)
PLLFB(0)
CKCR1
0702Eh
to
07031h
Reserved
A-to-D MODULE CONTROL REGISTERS
07032h
SUSPEND-
SOFT
SUSPEND-
FREE
ADCIM-
START
ADC1EN
ADC2EN
ADCCON-
RUN
ADCINTEN
ADCINTFLAG
ADCTRL1
ADCEOC
ADC2CHSEL
ADC1CHSEL
ADCSOC
07033h
Reserved
07034h
—
—
—
—
—
ADCEVSOC
ADCEXTSOC
—
ADCTRL2
ADCFIFO1
—
ADCFIFO2
ADCPSCALE
07035h
Reserved
07036h
D9
D8
D7
D6
D5
D4
D3
D2
ADCFIFO1
D1
D0
0
0
0
0
0
0
07037h
Reserved
07038h
D9
D8
D7
D6
D5
D4
D3
D2
ADCFIFO2
D1
D0
0
0
0
0
0
0
07039h
to
0703Fh
Reserved
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS
07040h
SPI SW
RESET
CLOCK
POLARITY
—
—
—
SPI
CHAR2
SPI
CHAR1
SPI
CHAR0
SPICCR
07041h
—
—
—
OVERRUN
INT ENA
CLOCK
PHASE
MASTER/
SLAVE
TALK
SPI INT
ENA
SPICTL
07042h
RECEIVER
OVERRUN
SPI INT
FLAG
—
—
—
—
—
—
SPISTS
07043h
Reserved
07044h
—
SPI BIT
RATE 6
SPI BIT
RATE 5
SPI BIT
RATE 4
SPI BIT
RATE 3
SPI BIT
RATE 2
SPI BIT
RATE 1
SPI BIT
RATE 0
SPIBRR
07045h
Reserved
07046h
ERCVD7
ERCVD6
ERCVD5
ERCVD4
ERCVD3
ERCVD2
ERCVD1
ERCVD0
SPIEMU
07047h
RCVD7
RCVD6
RCVD5
RCVD4
RCVD3
RCVD2
RCVD1
RCVD0
SPIBUF
07048h
Reserved
07049h
SDAT7
SDAT6
SDAT5
SDAT4
SDAT3
SDAT2
SDAT1
SDAT0
SPIDAT
0704Ah
to
0704Ch
Reserved
0704Dh
SPISTE
DATA IN
SPISTE
DATA OUT
SPISTE
FUNCTION
SPISTE
DATA DIR
SPICLK
DATA IN
SPICLK
DATA OUT
SPICLK
FUNCTION
SPICLK
DATA DIR
SPIPC1
0704Eh
SPISIMO
DATA IN
SPISIMO
DATA OUT
SPISIMO
FUNCTION
SPISIMO
DATA DIR
SPISOMI
DATA IN
SPISOMI
DATA OUT
SPISOMI
FUNCTION
SPISOMI
DATA DIR
SPIPC2
0704Fh
—
SPI
PRIORITY
SPI
ESPEN
—
—
—
—
—
SPIPRI