參數(shù)資料
型號(hào): TMS320C240PQQ
英文描述: 16-Bit Microcontroller
中文描述: 16位微控制器
文件頁(yè)數(shù): 80/105頁(yè)
文件大?。?/td> 1481K
代理商: TMS320C240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TIMING EVENT MANAGER INTERFACE
PWM/CMP timings
PWM refers to PWM1/CMP1, PWM2/CMP2, PWM3/CMP3, PWM4/CMP4, PWM5/CMP5, PWM6/CMP6,
T1PWM/T1CMP, T2PWM/T2CMP, T3PWM/T3CMP, PWM7/CMP7, PWM8/CMP8, and PWM9/CMP9.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t
c(CO)
] (see Figure 34)
PARAMETER
MIN
MAX
UNIT
td(PWM)CO
Delay time, CLKOUT high to PWM output switching
12
ns
timing requirements over recommended operating conditions for PWM timing [H = 0.5t
c(CO)
]
(see Figure 35 and Figure 36)
MIN
MAX
UNIT
tw(TMRDIR)
Pulse duration, TMRDIR low/high
4H + 12
4H + 14
ns
tw(TMRCLKL)
tw(TMRCLKH)
tc(TMRCLK)
MIN value for ’C240 only
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
40
60
%
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
40
60
%
Cycle time, TMRCLK
4
tc(CPU)
ns
td(PWM)CO
PWM
CLKOUT/IOPC1
Figure 34. PWM and Compare Output Timings
tw(TMRCLKL)
TMRCLK
tc(TMRCLK)
tw(TMRCLKH)
Figure 35. External Timer Clock Input Timings
tw(TMRDIR)
TMRDIR
Figure 36. External Timer Direction Input Timings
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