![](http://datasheet.mmic.net.cn/260000/TMS320F240PQA_datasheet_15975211/TMS320F240PQA_91.png)
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
91
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SPI slave mode external timing parameters (clock phase = 1)
(see Figure 46)
MIN
MAX
UNIT
tc(SPC)S
tw(SPCH)S§
tw(SPCL)S§
tw(SPCL)S§
tw(SPCH)S§
tsu(SOMI-SPCH)S§
tsu(SOMI-SPCL)S§
tv(SPCH-SOMI)S§
tv(SPCL-SOMI)S§
tsu(SIMO-SPCH)S§
tsu(SIMO-SPCL)S§
tv(SPCH-SIMO)S§
tv(SPCL-SIMO)S§
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Cycle time, SPICLK
8tc
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S–70
0.5tc(SPC)S–70
0.5tc(SPC)S–70
0.5tc(SPC)S–70
0.125tc(SPC)S
0.125tc(SPC)S
0.75tc(SPC)S
0.75tc(SPC)S
0
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
ns
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK high (clock polarity =0)
ns
Valid time, SPISOMI data valid after SPICLK low (clock polarity =1)
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
ns
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1)
0.5tc(SPC)S
0.5tc(SPC)S
ns