
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
95
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
ADC timing requirements (see Figure 48)
MIN
MAX
UNIT
tc(AD)
tw(SHC)
tw(SH)
tsu(SH)
th(SH)
tw(C)
td(SOC-SH)
td(EOC-FIFO)
Start of conversion is signaled by the ADCIMSTART bit or the ADCSOC bit set in software, the external start signal active (ADCSOC), or internal
EVSOC signal active.
NOTE 3: The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC-FIFO).
Cycle time, ADC prescaled clock
1
s
Pulse duration, total sample/hold and conversion time (see Note 3)
6.1
s
Pulse duration, sample and hold time
tc(AD)
0
s
Setup time, analog input stable before sample/hold start
ns
Hold time, analog input stable after sample/hold complete
0
ns
Pulse duration, total conversion time
Delay time, start of conversion to beginning of sample and hold
4.5tc(AD)
3tc(SYS)
3tc(SYS)
s
ns
Delay time, end of conversion to data loaded into result FIFO
ns
0
3
2
4
5
1
tw(C)
td(EOC–FIFO)
6
7
8
9
th(SH)
tw(SH)
tsu(SH)
tc(AD)
ADC Clock
Analog Input
Bit Converted
Convert
Internal Start
Start of Convert
XFR to FIFO
Sample/Hold
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Figure 48. Analog-to-Digital Timing
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