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| 型號： | TMPR3922AU |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32-bit RISC Microprocessor for PDA（Personal Digital Assistants)(32位 精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA) |
| 中文描述： | 32位RISC微處理器的PDA（個人數(shù)字助理）（32位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA）的 |
| 文件頁數(shù)： | 8/45頁 |
| 文件大?。?/td> | 343K |
| 代理商： | TMPR3922AU |
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2-FEB-1999
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TMPR3922AU
4.2 PIN FUNCTIONS
Memory Pins
NAME
D[31:0]
I/O
I/O
DESCRIPTION
These pins are the data bus for the system. 16-bit SDRAMs and DRAMs
should be connected to bits 15:0. All other 16-bit ports should be connected to
bits 31:16. Of course, 32-bit ports should be connected to be bits 31:0. These
pins are normally outputs and only become inputs during reads, thus no
resistors are required since the bus will only float for a short period of time
during bus turn-around.
These pins are the address bus for the system. The address lines are
multiplexed and can be connected directly to SDRAM and DRAM devices. To
generate the full 26-bit address for static devices, an external latch must be
used to latch the signals using the ALE signal. For static devices, address bits
25:13 are provided by the external latch and address bits 12:0 (directly
connected from the TMPR3922AU's address bus) are held afterward by the
TMPR3922AU for the remainder of the address bus cycle.
This pin is used as the address latch enable to latch A[12:0] using an external
latch, for generating the upper address bits 25:13.
This pin is used as the read signal for static devices. This signal is asserted for
reads from MC3*-0*, CS3*-0*, CARD2CS* and CARD1CS* for memory and
attribute space, and for reads from the TMPR3922AU accesses if SHOWDINO
is enabled (for debugging purposes) .
This pin is used as the write signal for system. This signal is asserted for writes
to MC3*-0*, CS3*-0*, CARD2CS* and CARD1CS* for memory and attribute
space, and for writes to DRAM and SDRAM.
This pin is used as the CAS signal for SDRAMs, the CAS signal for D[7:0] for
DRAMs, and the write enable signal for D[7:0] for static devices.
This pin is used as the CAS signal for D[15:8] for DRAMs, and the write enable
signal for D[15:8] for static devices.
This pin is used as the CAS signal for D[23:16] for DRAMs, and the write
enable signal for D[23:16] for static devices.
This pin is used as the CAS signal for D[31:24] for DRAMs, and the write
enable signal for D[31:24] for static devices.
This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0
DRAMs.
This pin is used as the chip select signal for Bank1 SDRAMs and the RAS
signal for Bank1 DRAMs.
A[12:0]
O
ALE
O
RD*
O
WE*
O
CAS0*(WE0*)
O
CAS1*(WE1*)
O
CAS2*(WE2*)
O
CAS3*(WE3*)
O
RAS0*
O
RAS1*(DCS1*)
O
*Active-low signal
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