參數(shù)資料
型號: TMPR3922AU
廠商: Toshiba Corporation
英文描述: 32-bit RISC Microprocessor for PDA(Personal Digital Assistants)(32位 精簡指令集系統(tǒng)計(jì)算機(jī)微處理器,用于掌上電腦PDA)
中文描述: 32位RISC微處理器的PDA(個(gè)人數(shù)字助理)(32位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器,用于掌上電腦PDA)的
文件頁數(shù): 23/45頁
文件大小: 343K
代理商: TMPR3922AU
2-FEB-1999
23
/
45
TMPR3922AU
5. FUNCTION SPECIFICATIONS
5.1 OUTLINE
The TMPR3922AU consists of PDA system support logic, integrated with the TX3920 Processor Core
designed by Toshiba. For details of the system support logic and the TX3920 processor Core, refer to
the TMPR3922AU User's manual and TX39 family user's manual, respectively.
5.2 TX3920 PROCESSOR CORE
The TX3920 processor core is a Toshiba-developed microprocessor core based on the R3000A RISC
architecture developed by The MIPS Group, a division of Silicon Graphics, Inc. of the United States.
5.2.1 INSTRUCTIONS
All TX3920 Processor Core instructions are 32-bit instructions. Apart from some coprocessor
instructions, the instructions are upwardly compatible with the R3000A. The TX3920 Processor Core
instructions can be classified into six types.
Load and store instructions
Transfer data between memory and general-purpose registers.
Computational instructions
These include arithmetic, logical, shift, multiply, divide, and multiply-add instructions. The
multiply-add instructions are extensions to the R3000A. The multiply instructions can also be
used as three-operand instructions.
Special instructions
Used for system call or break point.
Jump and branch instructions
Change the control flow of a program. The Branch-Likely instruction is provided as an extension
to the R3000A.
Coprocessor instructions
Perform operations for coprocessors. The R3000A LWCz and SWCz instructions are reserved
instructions in the TX3920 Processor Core. Attempting execution generates a reserved
instruction exception. Note that the COPz, CTCz and MTCz instructions are no-operation
instructions, the CFCz and MFCz instructions load undefined data to general purpose registers
(rt) in the TMPR3922AU.
System control coprocessor instructions
Perform operations on the CP0 registers to manipulate the memory management and exception
handling functions of the processor.
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