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參數(shù)資料
| 型號： | TMPR3922AU |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32-bit RISC Microprocessor for PDA（Personal Digital Assistants)(32位 精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA) |
| 中文描述： | 32位RISC微處理器的PDA（個(gè)人數(shù)字助理）（32位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA）的 |
| 文件頁數(shù)： | 13/45頁 |
| 文件大?。?/td> | 343K |
| 代理商： | TMPR3922AU |
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TMPR3922AU
SIB Pins
NAME
SIBDIN
I/O
I
DESCRIPTION
This pin contains the input data shifted from TC35143F and/or external codec
device.
This pin contains the output data shifted to TC35143F and/or external codec
device.
This pin is the serial clock sent to TC35143F and/or external codec device.
The programmable SIBSCLK rate is derived by dividing down from SIBMCLK.
This pin is the frame synchronization signal sent to TC35143F and/or external
codec device. This frame sync is asserted for one clock cycle immediately
before each frame starts and all devices connected to the SIB monitor
SIBSYNC to determine when they should transmit or receive data.
This pin is a general purpose input port used for the SIB interrupt source from
TC35143F. This interrupt source can be configured to generate an interrupt on
either a positive and/or negative edge.
This pin is the master clock source for the SIB logic. This pin is available for
use in one of two modes. First, SIBMCLK can be configured as a high-rate
output master clock source required by certain external codec devices. ln this
mode all SIB clocks are synchronously slaved to the main TMPR3922AU
system clock CLK2X. Conversely, SIBMCLK can be configured as an input
slave clock source. In this mode, all SIB clocks are derived from an external
SIBMCLK oscillator source, which is asynchronous with respect to CLK2X.
Also, for this mode, SIBMCLK can still be optionally used as a high-rate master
clock source required by certain external codec devices.
SIBDOUT
O
SIBSCLK
O
SIBSYNC
O
SIBIRQ
I
SIBMCLK
I/O
SPI Pins
NAME
SPICLK
I/O
I/O
DESCRIPTION
This pin is used to clock data in and out of either the SPI master or slave
device. This pin is the master clock source for the SPI logic. This pin is
available for use in one of two modes. First, SPICLK can be configured as a
master clock source required by certain external devices. In this mode all SPI
clocks are synchronously slaved to the main TMPR3922AU system clock
FREECLK. Conversely, SPICLK can be configured as an input slave clock
source. In this mode, all SPI clocks are derived from an external oscillator
source, which is asynchronous with respect to FREECLK.
This pin contains the data that is shifted into the SPI slave device .
This pin contains the data that is shifted out of the SPI slave device.
SPIOUT
SPIIN
O
I
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