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參數(shù)資料
| 型號： | TMP86PS64FG |
| 廠商： | Toshiba Corporation |
| 英文描述： | Zener Diode; Application: General; Pd (mW): 500; Vz (V): 6.9 to 7.2; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35 |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 27/210頁 |
| 文件大?。?/td> | 1455K |
| 代理商： | TMP86PS64FG |
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Page 17
TMP86PS64FG
2.2.3.1
Single-Clock Mode
In the single-clock mode, only the oscillator for high-frequency clock is used. The P21(XTIN) and P22
(XTOUT) pins for the low-frequency clock can be used as usual I/O ports. Since the main system clock is
generated from the high-frequency clock, the machine cycle time becomes 4/fc [s] in the single-clock
mode.
(1)
NORMAL1 mode
In the NORMAL1 mode, the CPU core and on-chip peripherals operate using the high-frequency
clock. After reset is released, NOMAL1 mode is entered.
(2)
IDLE1 mode
In the IDLE1 mode, the CPU and watchdog timer are halted, and on-chip peripherals are clocked
by the high-frequency clock. To enter the IDLE1 mode, set IDEL in the system control register 2
(SYSCR2) to 1. The IDLE1 mode is exited by the interrupt from the on-chip peripherals or external
interrupts, and returned to the NORMAL1 mode. When the IMF (interrupt master enable flag) is set
to 1 (interrupt enable), the normal operation is performed after the interrupt processing is completed.
When the IMF is set to 0 (interrupt disable), program execution resumes with the instruction immedi-
ately following the instruction that activated the IDLE1 mode.
(3)
IDLE0 mode
In the IDLE0 mode, the CPU and on-chip peripherals are halted except oscillator and TBT. The
IDEL0 mode is entered by setting the system control register SYSCR2<TGHALT> to 1 in the
NORMAL1 mode. When the IDLE0 mode is entered, the CPU is halted and the timing generator
stops clocking to the peripherals except TBT. When detecting the falling edge of the source clock set
in TBTCR<TBTCK>, the timing generator starts clocking to all on-chip peripherals.
When the IDLE0 mode is exited, the CPU restarts operation and returns to the NORMAL1 mode.
The IDLE0 mode is entered and returned to the NORMAL1 mode regardless of setting in
TBTCR<TBTEN>. Interrupt processing is performed when IMF = 1, EF8 (TBT interrupt enable
flag) = 1, and TBTCR<TBTEN> = 1.
When the IDLE0 mode is entered with TBTCR<TBTEN> = 1, INTTBT interrupt latch is set after
returning to the NORMAL mode.
2.2.3.2
Dual-Clock Mode
In the dual-clock mode, two oscillators for high-frequency and low-frequency are used. The P21
(XTIN) and P22 (XTOUT) pins are used for the low-frequency clock pins. (In the dual-clock mode, these
pins can not be used as I/O ports.) The main system clock is generated by the high-frequency clock in the
NORMAL2 and IDLE2 modes, and the low-frequency clock in the SLOW1/2 and SLEEP1/2 modes.
Therefore, the machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122
μ
s @
fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C series is put in the single-clock mode during reset. To use the dual-clock mode, oscil-
late the low-frequency clock at the top of the program.
(1)
NORMAL2 Mode
The CPU core operates with high-frequency clock. On-chip peripherals operate with high- and
low-frequency clocks.
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| TMP87C409BMG | Zener Diode; Application: General; Pd (mW): 500; Vz (V): 7.0 to 7.3; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35 |
| TMP87C409BNG | Zener Diode; Application: General; Pd (mW): 500; Vz (V): 7.2 to 7.6; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35 |
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