參數(shù)資料
型號(hào)： TLV5630EVM
廠商： Texas Instruments, Inc.
英文描述： TLV5630 Evaluation Module(TLC5630評(píng)估板)
中文描述： TLV5630評(píng)估模塊（TLC5630評(píng)估板）
文件頁數(shù)： 24/32頁
文件大小： 395K
代理商： TLV5630EVM
Processor Controlled Testing
3-6
3.2.4
Serial Clock
When the serial clock is supplied from an external host, jumper W18 must be
in position 2-3. The serial clock can be supplied via the common connector
interface at J11-21 or J6-3. Check the appropriate device data sheet for
maximum serial clock specifications.
3.2.5
Load DAC
The load DAC(/LDAC) pin is designed to simultaneously update all of the DAC
outputs with the current conversion data. This is an asynchronous pin that can
be held low permanently, if simultaneous updates are not required. This pin
is held at a low state by default on the EVM via pulldown resistor R27. This sig-
nal can be controlled through J9-5. DSP users can select to control /LDAC
from either DC_A13 at J10-13 or DC_CNTL0 at J11-64 through jumper W15.
3.2.6
MODE
Jumper W4 controls the signal level on the mode pin of U3 and U4. When
operated in DSP mode, W4 should be closed (MODE = 0). This causes the
DAC outputs to update after the 16
th
falling clock edge.
Opening W4 causes U3 and U4 to operate in microprocessor mode
(MODE = 1). In this condition, frame sync must be asserted high after the 16
th
falling clock edge, or the conversion will be lost.
3.2.7
Power Down
The four-channel device at U5 has a power-down pin that can be accessed
from J9-3. A low level on this pin will send the device into power-down mode.
DSP users can select either DC_CNTRL1 at J11-63 or DC_A12 via W16 as
the source of this control.
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TLV5630IDW 制造商:Texas Instruments 功能描述:IC's
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TLV5630IDWRG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 12-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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