參數(shù)資料
型號： TLV5630EVM
廠商： Texas Instruments, Inc.
英文描述： TLV5630 Evaluation Module(TLC5630評估板)
中文描述： TLV5630評估模塊（TLC5630評估板）
文件頁數(shù)： 10/32頁
文件大?。?/td> 395K
代理商： TLV5630EVM
EVM Basic Functions
1-4
Jumper block W2 is configured as follows:
Note:
Rows A0 and A1 are common to the EVM address bus. The center row is
connected to the DSP address bus via J10 pins 7 through 10. The following
diagram shows the C6000 address lines A14 and A15 connected to EVM A0
and A1 respectively.
A1
A0
A14
A15
A16
A17
DSP Address Lines
1.2.2.2
Address Function
Selection of the eight-channel DACs at U3 or U4 causes the frame sync and
the serial data stream to be directed to the chosen device. Selection of the
four-channel DAC at U5 puts a low-level signal on its chip select pin.
Address
Function
00
No selection made (default)
01
Selects U3 to receive frame sync
10
Selects U4 to receive frame sync
11
Selects U5 to receive chip select (active low signal)
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TLV5630IDW 制造商:Texas Instruments 功能描述:IC's
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