參數(shù)資料
型號: TLV5630EVM
廠商: Texas Instruments, Inc.
英文描述: TLV5630 Evaluation Module(TLC5630評估板)
中文描述: TLV5630評估模塊(TLC5630評估板)
文件頁數(shù): 22/32頁
文件大?。?/td> 395K
代理商: TLV5630EVM
Standalone Testing
3-4
3.1.4
Test Mode—TLV5630/31
Jumper W10 controls the eight-channel DAC at U3. This data converter can
be tested alone or in daisy chain mode with U4.
Switch bank SW4 serves two functions for these devices. During DAC write
cycles, SW4 selects the control register to be accessed. DAC write cycles are
initiated by setting bit D15.
TLV5630/31 Configuration Register 0:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
X
X
X
X
X
X
X
PD
DO
R1
R0
IM
PD: Full device power down
DO: Digital output enable
R1/R0: Reference Select
IM: Input Mode
X: Reserved
0 = Normal; 1 = Power Down
0 = Disable; 1 = Enable
00 = Ext., 01 = Ext., 10 = Int. 1 V, 11 = Int. 2 V
0 = Binary; 1 = 2s Complement
TLV5630/31 Configuration Register 1:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
X
X
X
X
PGH
PEF
PCD
PAB
SGH
SEF
SCD
SAB
PXY: Power down DACXY
Sxy: Speed DACXY
XY: DAC Pair AB, CD, EF, GH
0 = Normal;
0 = Slow
1 = Power Down
1 = Fast
During DAC read cycles, SW4 selects the output channel to be updated. DAC
read cycles are initiated by clearing bit D15.
TLV5610/08 Data Register:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
DAC Value
Channel Selection:
A3
A2
A1
A0
DAC/Output Connector
0
0
0
0
OUT A / J2–1
0
0
0
1
OUT B / J2–3
0
0
1
0
OUT C / J2–5
0
0
1
1
OUT D / J2–7
0
1
0
0
OUT E / J2–9
0
1
0
1
OUT F / J2–11
0
1
1
0
OUT G / J2–13
0
1
1
1
OUT H / J2–15
DAC Output Value:
Vout = 2Vref CODE/0x1000
Data bits D12 through D0 set the digital input code to be converted. Each bit
can be set independently by sliding the appropriate switch to the on position
(towards the middle of the EVM). Data is presented to the converter MSB first.
On the 10-bit TLV5631, data in locations D1 and D0 are ignored.
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