參數(shù)資料
型號(hào): TLV5614IYZR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, UUC16
封裝: GREEN, DIE-16
文件頁數(shù): 4/25頁
文件大?。?/td> 500K
代理商: TLV5614IYZR
www.ti.com
SERIAL CLOCK FREQUENCY AND UPDATE RATE
f
SCLKmax =
1
t
wH(min)
wL(min)
+t
=20MHz
f
=
UPDATEmax
1
16(t
+t
)
wH(min)
wL(min)
=1.25MHz
DATA FORMAT
SBAS401 – DECEMBER 2006
APPLICATION INFORMATION (continued)
Notes on SPI and Microwire connections: Before the controller starts the data transfer, the software must
generate a falling edge on the I/O pin connected to FS. If the word width is eight bits (SPI and Microwire), two
write operations must be performed to program the TLV5614IYZ. After the write operation(s), the DAC output is
updated automatically on the next positive clock edge following the 16th falling clock edge.
The maximum serial clock frequency is given by:
The maximum update rate is:
Note that the maximum update rate is a theoretical value for the serial interface, because the settling time of the
TLV5614IYZ must also be considered.
The 16-bit data word for the TLV5614IYZ consists of two parts:
Control bits (D15 . . . D12)
New DAC value (D11 . . . D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
New DAC value (12 bits)
X: don't care
SPD: Speed control bit. 1
→fast mode, 0→slow mode
PWR: Power control bit. 1
→power down, 0→normal operation
In power-down mode, all amplifiers within the TLV5614IYZ are disabled. A particular DAC (A, B, C, D) of the
TLV5614IYZ is selected by A1 and A0 within the input word.
A1
A0
DAC
0
A
0
1
B
1
0
C
1
D
12
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