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參數(shù)資料
| 型號： | TLV5614IYZR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, UUC16 |
| 封裝： | GREEN, DIE-16 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大小： | 500K |
| 代理商： | TLV5614IYZR |
www.ti.com
h(D)
1
2
3
4
5
15
16
D15
D14
D13
D12
D1
D0
t
su(FS-CK)
t
su(CS-FS)
t
wH(FS)
t
su(D)
t
wH
t
wL
t
su(C16-FS)
SCLK
DIN
CS
FS
t
su(C16-CS)
SBAS401 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT DYNAMIC PERFORMANCE
Fast
5
V/
s
CL = 100pF, RL = 10k, VO = 10% to 90%,
SR
Output slew rate
VREF = 2.048V, 1024V
Slow
1
V/
s
Fast
3
5.5
To
± 0.5 LSB, C
L = 100pF, RL = 10k, see
ts
Output settling time
s
(11) (12)
Slow
9
20
Fast
1
To
± 0.5 LSB, C
L = 100pF, RL = 10k, see
ts(c)
Output settling time, code to code
s
(13)
Slow
2
Glitch energy
Code transition from 7FF to 800
10
nV–s
SNR
Signal-to-noise ratio
74
Sinewave generated by DAC, Reference voltage =
SINAD
Signal to noise + distortion
66
1.024 at 3V and 2.048 at 5V, fS = 400KSPS, fOUT =
dB
1.1kHz sinewave, CL = 100pF, RL = 10k, BW =
THD
Total harmonic distortion
–68
20kHz
SFDR
Spurious-free dynamic range
70
DIGITAL INPUT TIMING REQUIREMENTS
tsu(CS–FS)
Setup time, CS low before FS
↓
10
ns
Setup time, FS low before first negative
tsu(FS–CK)
SCLK edge
8
ns
Setup time. 16th negative SCLK edge after FS low on which bit D0 is sampled before rising edge
tsu(C16–FS)
of FS
10
ns
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS is used
instead of the SCLK positive edge to update the DAC, then the setup time is between the FS rising
tsu(C16–CS)
edge and CS rising edge.
10
ns
twH
Pulse duration, SCLK high
25
ns
twL
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
Pulse duration, FS high
20
ns
(11) Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change of
FFFhex to 080hex for 080hex to FFFhex.
(12) Limits are ensured by design and characterization, but are not production tested.
(13) Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change of one
count.
Figure 1. Timing Diagram
4
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