參數(shù)資料
型號: TLK2201AIRCPR
廠商: Texas Instruments, Inc.
英文描述: ETHERNET TRANSCEIVERS
中文描述: 以太網(wǎng)收發(fā)器
文件頁數(shù): 3/21頁
文件大?。?/td> 343K
代理商: TLK2201AIRCPR
TLK2201A, TLK2201AI
ETHERNET TRANSCEIVERS
SLLS572
JUNE 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
block diagram
2:1
MUX
PRBS
Generator
10 Bit
Registers
TD(0
9)
PRBSEN
LOOPEN
Parallel to
Serial
Phase Generator
Clock
REFCLK
Control
Logic
MODESEL
ENABLE
TESTEN
Interpolator
and
Clock Extraction
PRBS
Verification
Serial to Parallel
and
Comma Detect
Clock
RBC1
RBC0
SYNC/PASS
RD(0
9)
SYNCEN
RBCMODE
JTAG
Control
Register
JTMS
JTRSTN
JTDI
TCK
JTDO
2:1
MUX
2:1
MUX
Clock
Data
TXP
TXN
RXP
RXN
LOS
detailed description
data transmission
These devices support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR
clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is
selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0
TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0
TD4. In this mode data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bit 0
4, and the falling edge of REFCLK clocks in bits
5
9. ( Bit 0 is the first bit transmitted).
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