參數(shù)資料
型號(hào)： TLE7242-2G
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： GREEN, PLASTIC, DSO-28
文件頁(yè)數(shù)： 7/50頁(yè)
文件大?。?/td> 1210K
代理商： TLE7242-2G
Data Sheet
15
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.2
Input / Output
All digital inputs are compatible with 3.3 V and 5 V I/O logic levels. The supply voltage for the SPI output SO is the
V_SIGNAL pin. All digital inputs are pulled to a known state by a weak internal current source or current sink when
not connected. However, unused digital input pins should be connected to ground or to V_SIGNAL (according to
the desired functionality) by an external connection or resistor. All input pin weak internal current sources are
supplied by the V_SIGNAL pin.
The RESET_B pin is an active low input pin. When this pin is low, all channels are off, and all internal registers
are reset to their default states. The device must be held in reset by an external source until all the power supplies
have stabilized. The IC contains an internal power on and undervoltage reset which becomes active when V5D or
V5A fall below the undervoltage reset threshold (VUVA, VUVD).
The ENABLE pin is an active high input pin which must be held high for normal operation of the device. When this
pin is held low all channels are either turned off or will remain in the last state, depending on how the enable
behavior of the channel is programmed via SPI. The default condition is that all channels are turned off when the
ENABLE pin is low.
The CLK pin is the main clock input for the device. The input thresholds are compatible with 3.3 V and 5.0 V logic
levels. No synchronization is required between the clock signal connected to the CLK pin and the SPI clock signal
(SCK). All frequencies of operation (PWM signals, A/D sampling, diagnostics, etc.) are based on this clock input.
Also, this clock is required in order for the device to accept and respond to SPI messages.
Figure 9
CLK Timing Diagram
The PHASE_SYNC pin is an input pin that can be used by the microcontroller to synchronize the PWM control
signals of multiple channels. The desired phase delay between the rising edge of the signal applied to the
PHASE_SYNC pin and the rising edge of the PWM signal of each channel can be programmed independently via
SPI message #2. The equation for calculating the offset is:
Each time the phase sequence occurs, the IC will latch a bit which is reported via the response to SPI message
#11. (See SPI interface section for bit/message location.) This latch is cleared when the message is read.
Note: The PWM periods are restarted when a rising edge is detected on the PHASE_SYNC pin. A periodic pulse
train on this pin will disturb the current regulation.
CLK
t
14
1/f
clk
t
15
VIH
min
VIL
max
PWM
offset
F
Offset
PhaseSynch
T
*
32
=
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