參數(shù)資料
型號： TLE7242-2G
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： GREEN, PLASTIC, DSO-28
文件頁數(shù)： 3/50頁
文件大小： 1210K
代理商： TLE7242-2G
Data Sheet
11
Rev. 1.0, 2008-07-09
TLE7242-2G
Pin Configuration
10
NEG1
I
A
Channel #1 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
11
NEG0
I
A
Channel #0 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
12
POS0
I
A
Channel #0 Positive sense pin. Connect to the "load" side of the
external sense resistor.
13
OUT1
O
A
Gate driver output for channel #1. Connect to the gate of the
external MOSFET.
14
OUT0
O
A
Gate driver output for channel #0. Connect to the gate of the
external MOSFET.
15
BAT
I
A
Battery sense input for over voltage detection. Connect through a
series resistor (e.g. 1 Kohm) to the solenoid supply voltage. A
large electrolytic capacitor (e.g. 47uF) should be placed between
the BAT supply and ground.
16
PHASE_SYNC
I
D
Used to synchronize the rising edges of the PWM signal on the
OUTx pins for each channel.
17
TEST
I
D
Used for IC Test. Must be connected to GND_D for specified
operation of the IC.
18
SI
I
D
SPI Serial data in
19
V_SIGNAL
I
-
Supply pin for the SPI SO output and the pull-ups of the digital
inputs CS_B and RESET_B. An external capacitor must be con-
nected between this pin and GND_D near this pin.
20
SO
O
D
SPI Serial data out
21
GND_D
-
GND pin for digital and driver circuitry.
22
CLK
I
D
Main clock input for the IC. A clock input of 20 MHz to 40 MHz is
required.
23
V5D
-
5V supply pin for the digital circuit blocks and the OUT pin driver
circuits. A pair of external capacitors is to be connected between
this pin and GND_D very near this pin. Example values of the
external capacitors are 100nF and 100pF.
24
SCK
I
D
SPI Clock input
25
CS_B
I
D
SPI Chip Select Bar (low active signal)
26
ENABLE
I
D
When this input pin is low all channels are turned off (zero current)
or remain in their last state, depending on how the channel is
programmed to respond
27
RESET_B
I
D
When this input pin is low all channels are turned off and all
internal registers are reset to their default state. The part must be
held in reset by an external source until all supplies are stable and
within tolerance.
28
FAULT
O
D
This open drain output pin is pulled low when a fault condition is
detected. Certain faults can be masked via SPI.
Pin
Symbol
I/O
Analog
/Digital
Function
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