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參數(shù)資料
| 型號： | TLC34076-85 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(85MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（85MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 24/56頁 |
| 文件大?。?/td> | 419K |
| 代理商： | TLC34076-85 |
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2-12
Table 2-7. True-Color Mode
DATA
BITS PER
PIXEL
1
0
MODE
MUX CONTROL REGISTER BITS
PIXEL
BUS
WIDTH
SCLK
DIVIDE
RATIO§
OVERLAY
BITS PER
PIXEL (4)
PIXEL
LATCHING
SEQUENCE
5
4
3
2
6
6a
6b
0
0
0
0
1
1
0
0
0
0
0
1
15
16
16
16
1
1
1
1) P<15:0>
1) P<15:0>
1) P<15:0>
2) P<31:16>
1) P<15:0>
2) P<31:16>
1) P<31:0>
1) P<31:0>
N/A
6c
0
0
1
0
0
0
15
32
2
1
6d
0
0
1
0
1
1
16
32
2
N/A
6e
6f
0
0
0
0
1
1
1
1
1
0
0
1
24
24
32
32
1
1
8
8
Bits 6 and 7 are don’t carebits.
This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,
often referred to as the number of bit planes. This may be color palette address data (Modes 0–5) or DAC data
(Mode 6).
§The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per
bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8
bit planes, 4 pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but must
be written to the output clock selection register.
For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 6d with a 32-bit pixel bus width, the rising edge of SCLK latches all the data
groups, and the pixel clock shifts them out in the order P<15:0>, P<31:16>.
#Mode 6 is true color mode, in which 24 bits of color information are transferred directly from the pixel port to the DACs;
overlay is implemented with the remaining 8 bits of the pixel bus. The distribution of pixel port data to the DACs is as
follows: P<31:24> are passed to the blue DAC, P<23:16> are passed to the green DAC, and P<15:8> are passed to
the red DAC. P<7:0> are used to generate overlay data; this operation can be disabled by either grounding P<7:0> or
by clearing the read mask (see Section 2.4.6).
NOTE: Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground lowers
power consumption and, thus, is recommended.
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