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參數(shù)資料
| 型號： | TLC34076-85 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(85MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（85MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 419K |
| 代理商： | TLC34076-85 |
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FUNCTION
2-3
power-up is CLK0; an alternative source can be selected by software during normal operation. This chosen
clock input is used unmodified as the dot clock (representing the pixel rate to the monitor). The device does,
however, allow for user programming of the SCLK and VCLK outputs (shift and video clocks) via the output
clock selection register. The input/output clock selection registers are shown in Tables 2–3, 2–4, and 2–5.
The ECL input can be used as a differential or single-ended input. If the CLK3 input is used as a single-ended
ECL input, the CLK3 input must be externally terminated to set the input common-mode signal level. This
can be done with a simple resistor divider, as is the case with fully differential ECL.
SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals like
BLANK and SYNC’s. While SCLK and VCLK are designed as general-purpose shift clock and video clock,
respectively, they also interface directly with the TMS340x0 GSP family directly. Even though SCLK and
VCLK can be selected independently, there is still a relationship between the two as discussed below. Many
system considerations hve been carefully covered in the design, leaving maximum freedom to the user.
Internally, both SCLK and VCLK are generated from a common clock counter that increments on the rising
edge of the DOTCLK. Therefore, when VCLK is enabled, it is in phase with SCLK (see Figure 2–1).
The internal clock counter is initialized to value 0 any time the output clock-selection register (bits 5, 4, 2,
1) are all set to 1’s. This provides a simple mechanism to synchronize multiple Video Interface Palettes, by
providing a known phase relationship for the various system clocks. One can write directly to the Output
Clock Selection Register to cause this to occur, or any of the various resets (POR, Hardware, Software–see
section 1.5) will also cause the appropriate bits to be written and the counters to reset. It is up to the user
to provide some means of disabling the dot-clock input to the part while this reset is occurring, if multiple
parts are to be synchronized.
Appendix A discusses the SCLK/VCLK relationship specific to the TMS340x0 GSP.
as an example)
(DOTCLK/2
SCLK
as an example)
(DOTCLK/4
VCLK
DOTCLK
Figure 2–1. DOTCLK/VCLK/SCLK Relationship
Table 2–3. Input Clock Selection Register Format
BITS
2
0
0
0
0
1
0
3
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
Select CLK0 as clock source§
Select CLK1 as clock source
Select CLK2 as clock source
Select CLK3 as TTL clock source
Select CLK3 as TTL clock source
Select CLK3 and CLK3 as ECL clock sources
Register bits 4, 5, 6, and 7 are don’t care bits.
When the clock selection is altered, a minimum 30-ns delay is incurred before the
new clocks are stabilized and running.
§CLK0 is chosen at power-up to support the VGA pass-through mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34076-85FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
| TLC352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352CD | 功能描述:校驗器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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